{"id":"https://openalex.org/W2911336408","doi":"https://doi.org/10.1109/mwscas.2018.8623928","title":"A Digital PLL Based 2<sup>nd</sup>-Order \u0394\u2211 Bandpass Time-Interleaved ADC","display_name":"A Digital PLL Based 2<sup>nd</sup>-Order \u0394\u2211 Bandpass Time-Interleaved ADC","publication_year":2018,"publication_date":"2018-08-01","ids":{"openalex":"https://openalex.org/W2911336408","doi":"https://doi.org/10.1109/mwscas.2018.8623928","mag":"2911336408"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas.2018.8623928","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2018.8623928","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5057502115","display_name":"Sanjeev Tannirkulam Chandrasekaran","orcid":"https://orcid.org/0000-0002-2162-7676"},"institutions":[{"id":"https://openalex.org/I63190737","display_name":"University at Buffalo, State University of New York","ror":"https://ror.org/01y64my43","country_code":"US","type":"education","lineage":["https://openalex.org/I63190737"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sanjeev Tannirkulam Chandrasekaran","raw_affiliation_strings":["Electrical Engineering Department, The State University of New York at Buffalo, Buffalo, NY"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical Engineering Department, The State University of New York at Buffalo, Buffalo, NY","institution_ids":["https://openalex.org/I63190737"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5005496543","display_name":"Arindam Sanyal","orcid":"https://orcid.org/0000-0003-4045-6291"},"institutions":[{"id":"https://openalex.org/I63190737","display_name":"University at Buffalo, State University of New York","ror":"https://ror.org/01y64my43","country_code":"US","type":"education","lineage":["https://openalex.org/I63190737"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Arindam Sanyal","raw_affiliation_strings":["Electrical Engineering Department, The State University of New York at Buffalo, Buffalo, NY"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical Engineering Department, The State University of New York at Buffalo, Buffalo, NY","institution_ids":["https://openalex.org/I63190737"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I63190737"],"apc_list":null,"apc_paid":null,"fwci":0.5183,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.65523535,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"286","last_page":"289"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/integrator","display_name":"Integrator","score":0.7749300599098206},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.682619571685791},{"id":"https://openalex.org/keywords/ring-oscillator","display_name":"Ring oscillator","score":0.671434760093689},{"id":"https://openalex.org/keywords/successive-approximation-adc","display_name":"Successive approximation ADC","score":0.6570776104927063},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6260955929756165},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.6231144070625305},{"id":"https://openalex.org/keywords/noise-shaping","display_name":"Noise shaping","score":0.5936470031738281},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5198993682861328},{"id":"https://openalex.org/keywords/quantization","display_name":"Quantization (signal processing)","score":0.4634535014629364},{"id":"https://openalex.org/keywords/effective-number-of-bits","display_name":"Effective number of bits","score":0.45011672377586365},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.4379955530166626},{"id":"https://openalex.org/keywords/transfer-function","display_name":"Transfer function","score":0.43496376276016235},{"id":"https://openalex.org/keywords/matlab","display_name":"MATLAB","score":0.43439921736717224},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.3981180191040039},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.31012383103370667},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.27644670009613037},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2411414086818695},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.11079579591751099},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10660234093666077},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.10280728340148926}],"concepts":[{"id":"https://openalex.org/C79518650","wikidata":"https://www.wikidata.org/wiki/Q2081431","display_name":"Integrator","level":3,"score":0.7749300599098206},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.682619571685791},{"id":"https://openalex.org/C104111718","wikidata":"https://www.wikidata.org/wiki/Q2153973","display_name":"Ring oscillator","level":3,"score":0.671434760093689},{"id":"https://openalex.org/C60154766","wikidata":"https://www.wikidata.org/wiki/Q2650458","display_name":"Successive approximation ADC","level":4,"score":0.6570776104927063},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6260955929756165},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6231144070625305},{"id":"https://openalex.org/C9083635","wikidata":"https://www.wikidata.org/wiki/Q2133535","display_name":"Noise shaping","level":2,"score":0.5936470031738281},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5198993682861328},{"id":"https://openalex.org/C28855332","wikidata":"https://www.wikidata.org/wiki/Q198099","display_name":"Quantization (signal processing)","level":2,"score":0.4634535014629364},{"id":"https://openalex.org/C16671190","wikidata":"https://www.wikidata.org/wiki/Q505579","display_name":"Effective number of bits","level":3,"score":0.45011672377586365},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.4379955530166626},{"id":"https://openalex.org/C81299745","wikidata":"https://www.wikidata.org/wiki/Q334269","display_name":"Transfer function","level":2,"score":0.43496376276016235},{"id":"https://openalex.org/C2780365114","wikidata":"https://www.wikidata.org/wiki/Q169478","display_name":"MATLAB","level":2,"score":0.43439921736717224},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.3981180191040039},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.31012383103370667},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.27644670009613037},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2411414086818695},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.11079579591751099},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10660234093666077},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.10280728340148926},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mwscas.2018.8623928","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2018.8623928","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.4300000071525574,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1511579013","https://openalex.org/W1991012581","https://openalex.org/W2000599207","https://openalex.org/W2030040019","https://openalex.org/W2039475683","https://openalex.org/W2071484340","https://openalex.org/W2097311800","https://openalex.org/W2110686269","https://openalex.org/W2124393408","https://openalex.org/W2143905081","https://openalex.org/W2153118630","https://openalex.org/W2153293882","https://openalex.org/W6674528230","https://openalex.org/W6676295223","https://openalex.org/W6682940424"],"related_works":["https://openalex.org/W2914701507","https://openalex.org/W2982541868","https://openalex.org/W3176856240","https://openalex.org/W3011208887","https://openalex.org/W2905521207","https://openalex.org/W2580320552","https://openalex.org/W3002516890","https://openalex.org/W2909877441","https://openalex.org/W2487410127","https://openalex.org/W1526838648"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,10,20,86],"time-interleaved":[4],"(TI)":[5],"VCObased":[6],"band-pass":[7,42],"ADC":[8,18,43,58,77],"with":[9],"second-order":[11],"bandstop":[12],"noise":[13],"transfer":[14],"function.":[15],"The":[16,56,75],"proposed":[17,41,57,76],"uses":[19],"digital":[21],"phase-locked":[22],"loop":[23],"(PLL)":[24],"based":[25],"architecture":[26],"and":[27,50,54,64,66,84],"employs":[28],"current":[29],"starved":[30],"ring-oscillator":[31],"as":[32],"integrator":[33],"which":[34],"provides":[35],"inherent":[36],"multi-bit":[37],"quantization.":[38],"Thus,":[39],"the":[40,73],"does":[44],"not":[45],"need":[46],"op-amps":[47],"for":[48],"integration":[49],"consumes":[51],"low":[52],"power":[53],"area.":[55],"is":[59],"designed":[60],"in":[61],"65nm":[62],"CMOS":[63],"Matlab":[65],"Spectre":[67],"simulations":[68],"were":[69],"performed":[70],"to":[71],"characterize":[72],"ADC.":[74],"achieves":[78],"61dB":[79],"SNDR":[80],"while":[81],"consuming":[82],"0.44mW":[83],"has":[85],"Walden":[87],"FoM":[88],"of":[89],"63fJ/conv.":[90],"step.":[91]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
