{"id":"https://openalex.org/W2940272074","doi":"https://doi.org/10.1109/mwscas.2018.8623910","title":"MCML Dynamic Register Design","display_name":"MCML Dynamic Register Design","publication_year":2018,"publication_date":"2018-08-01","ids":{"openalex":"https://openalex.org/W2940272074","doi":"https://doi.org/10.1109/mwscas.2018.8623910","mag":"2940272074"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas.2018.8623910","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2018.8623910","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5022476734","display_name":"Neeta Pandey","orcid":"https://orcid.org/0000-0003-2911-7061"},"institutions":[{"id":"https://openalex.org/I863896202","display_name":"Delhi Technological University","ror":"https://ror.org/01ztcvt22","country_code":"IN","type":"education","lineage":["https://openalex.org/I863896202"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Neeta Pandey","raw_affiliation_strings":["Delhi Technological University, New Delhi, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Delhi Technological University, New Delhi, India","institution_ids":["https://openalex.org/I863896202"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082620922","display_name":"Kirti Gupta","orcid":"https://orcid.org/0000-0003-0565-0654"},"institutions":[{"id":"https://openalex.org/I887998513","display_name":"Bharati Vidyapeeth Deemed University","ror":"https://ror.org/0052mmx10","country_code":"IN","type":"education","lineage":["https://openalex.org/I887998513"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Kirti Gupta","raw_affiliation_strings":["Bharati Vidyapeeth's College of Engineering, New Delhi, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Bharati Vidyapeeth's College of Engineering, New Delhi, India","institution_ids":["https://openalex.org/I887998513"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5019332578","display_name":"Bharat Choudhary","orcid":"https://orcid.org/0000-0002-7311-1815"},"institutions":[{"id":"https://openalex.org/I863896202","display_name":"Delhi Technological University","ror":"https://ror.org/01ztcvt22","country_code":"IN","type":"education","lineage":["https://openalex.org/I863896202"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Bharat Choudhary","raw_affiliation_strings":["Delhi Technological University, New Delhi, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Delhi Technological University, New Delhi, India","institution_ids":["https://openalex.org/I863896202"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.1309,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.53344329,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"582","last_page":"586"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.8058590888977051},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.7533594369888306},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6945748329162598},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.6478062868118286},{"id":"https://openalex.org/keywords/shift-register","display_name":"Shift register","score":0.6059646010398865},{"id":"https://openalex.org/keywords/waveform","display_name":"Waveform","score":0.5046361684799194},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.49071204662323},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.45962584018707275},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.45823174715042114},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.44891270995140076},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.43516111373901367},{"id":"https://openalex.org/keywords/register","display_name":"Register (sociolinguistics)","score":0.41070273518562317},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3772260546684265},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3408699035644531},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.22770655155181885},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19877222180366516},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.13297978043556213},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.08055123686790466},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.06729912757873535}],"concepts":[{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.8058590888977051},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.7533594369888306},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6945748329162598},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.6478062868118286},{"id":"https://openalex.org/C49654631","wikidata":"https://www.wikidata.org/wiki/Q746165","display_name":"Shift register","level":3,"score":0.6059646010398865},{"id":"https://openalex.org/C197424946","wikidata":"https://www.wikidata.org/wiki/Q1165717","display_name":"Waveform","level":3,"score":0.5046361684799194},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.49071204662323},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.45962584018707275},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.45823174715042114},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.44891270995140076},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.43516111373901367},{"id":"https://openalex.org/C2779235478","wikidata":"https://www.wikidata.org/wiki/Q286576","display_name":"Register (sociolinguistics)","level":2,"score":0.41070273518562317},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3772260546684265},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3408699035644531},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.22770655155181885},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19877222180366516},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.13297978043556213},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.08055123686790466},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.06729912757873535},{"id":"https://openalex.org/C554190296","wikidata":"https://www.wikidata.org/wiki/Q47528","display_name":"Radar","level":2,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mwscas.2018.8623910","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2018.8623910","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Decent work and economic growth","score":0.4699999988079071,"id":"https://metadata.un.org/sdg/8"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1595570256","https://openalex.org/W2049947650","https://openalex.org/W2082710254","https://openalex.org/W2124801118","https://openalex.org/W2134830891","https://openalex.org/W2153083613","https://openalex.org/W2157955314","https://openalex.org/W2219751636","https://openalex.org/W2543007092","https://openalex.org/W2612120119","https://openalex.org/W3103339143","https://openalex.org/W4230728857","https://openalex.org/W6737362722"],"related_works":["https://openalex.org/W4247180033","https://openalex.org/W2088914741","https://openalex.org/W2559451387","https://openalex.org/W2040807843","https://openalex.org/W4249038728","https://openalex.org/W1999924508","https://openalex.org/W3006003651","https://openalex.org/W4247089581","https://openalex.org/W2144282137","https://openalex.org/W2617666058"],"abstract_inverted_index":{"This":[0],"paper":[1,20],"proposes":[2],"MOS":[3],"current":[4],"mode":[5],"logic":[6],"(MCML)":[7],"dynamic":[8],"register.":[9],"The":[10,19,52,71],"register":[11,72],"employs":[12],"tristate":[13],"buffers":[14],"working":[15],"in":[16],"master-slave":[17],"configuration.":[18],"also":[21,103],"investigates":[22],"the":[23,26,39,61,65,69,96,99],"behavior":[24,49],"of":[25,68,98],"registers":[27],"on":[28,57],"clock":[29,46,78],"overlap":[30],"and":[31,74],"finds":[32],"that":[33],"it":[34],"do":[35],"not":[36],"comply":[37],"with":[38],"desired":[40],"functionality.":[41],"Two":[42],"techniques":[43,101],"to":[44,94],"achieve":[45],"skew":[47,79],"insensitive":[48],"are":[50,80,102],"proposed.":[51],"first":[53],"technique":[54,63],"puts":[55],"constraints":[56],"timing":[58,92],"parameter":[59],"whereas":[60],"second":[62],"modifies":[64],"enabling":[66],"mechanism":[67],"buffer.":[70],"operation":[73],"their":[75],"insensitivity":[76],"towards":[77],"examined":[81],"through":[82],"simulations":[83],"using":[84],"TSMC":[85],"90":[86],"nm":[87],"CMOS":[88],"technology":[89],"parameters.":[90],"Various":[91],"waveforms":[93],"demonstrate":[95],"effectiveness":[97],"proposed":[100],"included.":[104]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":4},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2021,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}