{"id":"https://openalex.org/W2757282635","doi":"https://doi.org/10.1109/mwscas.2017.8053215","title":"Tunneling transistor based 6T SRAM bitcell circuit design in sub-10nm domain","display_name":"Tunneling transistor based 6T SRAM bitcell circuit design in sub-10nm domain","publication_year":2017,"publication_date":"2017-08-01","ids":{"openalex":"https://openalex.org/W2757282635","doi":"https://doi.org/10.1109/mwscas.2017.8053215","mag":"2757282635"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas.2017.8053215","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2017.8053215","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5082164731","display_name":"Nahid M. Hossain","orcid":null},"institutions":[{"id":"https://openalex.org/I4210119942","display_name":"Wuhan Textile University","ror":"https://ror.org/02jgsf398","country_code":"CN","type":"education","lineage":["https://openalex.org/I4210119942"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Nahid Hossain","raw_affiliation_strings":["College of Computer Science, Wuhan Textile University, Wuhan, China"],"affiliations":[{"raw_affiliation_string":"College of Computer Science, Wuhan Textile University, Wuhan, China","institution_ids":["https://openalex.org/I4210119942"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101632804","display_name":"Ar\u0131f Iqbal","orcid":"https://orcid.org/0000-0002-7113-6007"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Arif Iqbal","raw_affiliation_strings":[],"affiliations":[]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077047345","display_name":"Hemanshu Shishupal","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Hemanshu Shishupal","raw_affiliation_strings":[],"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5075580787","display_name":"Masud H. Chowdhury","orcid":"https://orcid.org/0000-0002-2341-8528"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Masud H Chowdhury","raw_affiliation_strings":[],"affiliations":[]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5082164731"],"corresponding_institution_ids":["https://openalex.org/I4210119942"],"apc_list":null,"apc_paid":null,"fwci":0.2867,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.59768272,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1485","last_page":"1488"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.8317555785179138},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.6953216791152954},{"id":"https://openalex.org/keywords/quantum-tunnelling","display_name":"Quantum tunnelling","score":0.5555068254470825},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.5034818053245544},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4717365503311157},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4653151035308838},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4570664167404175},{"id":"https://openalex.org/keywords/domain","display_name":"Domain (mathematical analysis)","score":0.45405369997024536},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3610624074935913},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3529745936393738},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.2953263819217682},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.2753804922103882},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20338812470436096},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.15196317434310913},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.1515701413154602}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.8317555785179138},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.6953216791152954},{"id":"https://openalex.org/C120398109","wikidata":"https://www.wikidata.org/wiki/Q175751","display_name":"Quantum tunnelling","level":2,"score":0.5555068254470825},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.5034818053245544},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4717365503311157},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4653151035308838},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4570664167404175},{"id":"https://openalex.org/C36503486","wikidata":"https://www.wikidata.org/wiki/Q11235244","display_name":"Domain (mathematical analysis)","level":2,"score":0.45405369997024536},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3610624074935913},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3529745936393738},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.2953263819217682},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.2753804922103882},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20338812470436096},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.15196317434310913},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.1515701413154602},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mwscas.2017.8053215","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2017.8053215","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8799999952316284,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1590265419","https://openalex.org/W1860306208","https://openalex.org/W2051913544","https://openalex.org/W2094935094","https://openalex.org/W2469984388","https://openalex.org/W2516816469","https://openalex.org/W4231727700","https://openalex.org/W6725492686"],"related_works":["https://openalex.org/W2135546725","https://openalex.org/W2089002058","https://openalex.org/W1909296377","https://openalex.org/W3185029353","https://openalex.org/W2969498307","https://openalex.org/W3116379964","https://openalex.org/W2915176329","https://openalex.org/W2793465010","https://openalex.org/W2208608937","https://openalex.org/W2120018824"],"abstract_inverted_index":{"The":[0,84],"Static":[1],"Random":[2],"Access":[3],"Memory":[4],"(SRAM)":[5],"directly":[6],"impacts":[7],"the":[8,11,16,53,74,105],"performance":[9,18,85],"of":[10,46],"modern":[12],"multi-core":[13],"processor.":[14],"Hence,":[15],"power,":[17,77,81,97],"and":[19,89],"area":[20],"metrics":[21,100],"are":[22,92,101],"very":[23],"crucial":[24],"for":[25,55],"SRAM":[26,40,68],"design.":[27],"In":[28],"this":[29],"article,":[30],"we":[31,71],"have":[32,51,72],"successfully":[33],"designed":[34],"10":[35],"nm":[36],"TFET":[37],"based":[38],"6T":[39,67],"circuit":[41,54],"at":[42],"reduced":[43],"supply":[44],"voltage":[45],"0.5":[47],"V.":[48],"We":[49],"also":[50,93,102],"optimized":[52],"high":[56,58,63,65],"density,":[57,64],"performance,":[59],"intermediate":[60],"(trade-off":[61],"between":[62],"performance)":[66],"application.":[69],"Later,":[70],"estimated":[73],"dynamic":[75],"\u201cRead\u201d":[76,78,87],"energy,":[79,98],"\u201cWrite\u201d":[80,82],"energy.":[83],"metrics:":[86],"delay":[88,99],"\u201cWrite":[90],"delay\u201d":[91],"analyzed":[94],"precisely.":[95],"These":[96],"compared":[103],"against":[104],"existing":[106],"10nm":[107],"FinFET.":[108]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
