{"id":"https://openalex.org/W2759700740","doi":"https://doi.org/10.1109/mwscas.2017.8053199","title":"A hybrid memristor-CMOS multiplier design based on memristive universal logic gates","display_name":"A hybrid memristor-CMOS multiplier design based on memristive universal logic gates","publication_year":2017,"publication_date":"2017-08-01","ids":{"openalex":"https://openalex.org/W2759700740","doi":"https://doi.org/10.1109/mwscas.2017.8053199","mag":"2759700740"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas.2017.8053199","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2017.8053199","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5058570407","display_name":"Mehri Teimoory","orcid":null},"institutions":[{"id":"https://openalex.org/I74413500","display_name":"University of Windsor","ror":"https://ror.org/01gw3d370","country_code":"CA","type":"education","lineage":["https://openalex.org/I74413500"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Mehri Teimoory","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Windsor, Windsor, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Windsor, Windsor, Canada","institution_ids":["https://openalex.org/I74413500"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5012864861","display_name":"Amirali Amirsoleimani","orcid":"https://orcid.org/0000-0001-5760-6861"},"institutions":[{"id":"https://openalex.org/I74413500","display_name":"University of Windsor","ror":"https://ror.org/01gw3d370","country_code":"CA","type":"education","lineage":["https://openalex.org/I74413500"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Amirali Amirsoleimani","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Windsor, Windsor, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Windsor, Windsor, Canada","institution_ids":["https://openalex.org/I74413500"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100833525","display_name":"Arash Ahmadi","orcid":"https://orcid.org/0000-0001-5094-5967"},"institutions":[{"id":"https://openalex.org/I74413500","display_name":"University of Windsor","ror":"https://ror.org/01gw3d370","country_code":"CA","type":"education","lineage":["https://openalex.org/I74413500"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Arash Ahmadi","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Windsor, Windsor, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Windsor, Windsor, Canada","institution_ids":["https://openalex.org/I74413500"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5035412745","display_name":"Majid Ahmadi","orcid":"https://orcid.org/0000-0001-5781-6754"},"institutions":[{"id":"https://openalex.org/I74413500","display_name":"University of Windsor","ror":"https://ror.org/01gw3d370","country_code":"CA","type":"education","lineage":["https://openalex.org/I74413500"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Majid Ahmadi","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Windsor, Windsor, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Windsor, Windsor, Canada","institution_ids":["https://openalex.org/I74413500"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5058570407"],"corresponding_institution_ids":["https://openalex.org/I74413500"],"apc_list":null,"apc_paid":null,"fwci":0.8764,"has_fulltext":false,"cited_by_count":26,"citation_normalized_percentile":{"value":0.76531565,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1422","last_page":"1425"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9965000152587891,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/memristor","display_name":"Memristor","score":0.904141902923584},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.654190182685852},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6486219763755798},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.6157591342926025},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.6143451929092407},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.585279643535614},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5505636930465698},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.4895099401473999},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.47462618350982666},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.46115824580192566},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.42813417315483093},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4255889058113098},{"id":"https://openalex.org/keywords/and-or-invert","display_name":"AND-OR-Invert","score":0.42057564854621887},{"id":"https://openalex.org/keywords/memistor","display_name":"Memistor","score":0.41324567794799805},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3949495851993561},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2586301565170288},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21594193577766418},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.192884624004364},{"id":"https://openalex.org/keywords/resistive-random-access-memory","display_name":"Resistive random-access memory","score":0.17308062314987183},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.09716686606407166}],"concepts":[{"id":"https://openalex.org/C150072547","wikidata":"https://www.wikidata.org/wiki/Q212923","display_name":"Memristor","level":2,"score":0.904141902923584},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.654190182685852},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6486219763755798},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.6157591342926025},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.6143451929092407},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.585279643535614},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5505636930465698},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.4895099401473999},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.47462618350982666},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.46115824580192566},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.42813417315483093},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4255889058113098},{"id":"https://openalex.org/C130126468","wikidata":"https://www.wikidata.org/wiki/Q4652943","display_name":"AND-OR-Invert","level":5,"score":0.42057564854621887},{"id":"https://openalex.org/C1895703","wikidata":"https://www.wikidata.org/wiki/Q6034938","display_name":"Memistor","level":4,"score":0.41324567794799805},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3949495851993561},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2586301565170288},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21594193577766418},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.192884624004364},{"id":"https://openalex.org/C182019814","wikidata":"https://www.wikidata.org/wiki/Q1143830","display_name":"Resistive random-access memory","level":3,"score":0.17308062314987183},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.09716686606407166},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mwscas.2017.8053199","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2017.8053199","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W86283768","https://openalex.org/W845285418","https://openalex.org/W1953553490","https://openalex.org/W1986623396","https://openalex.org/W2004782555","https://openalex.org/W2064632620","https://openalex.org/W2066280488","https://openalex.org/W2081729575","https://openalex.org/W2083537989","https://openalex.org/W2112181056","https://openalex.org/W2335248059","https://openalex.org/W2515101082","https://openalex.org/W2547440906","https://openalex.org/W2569842290","https://openalex.org/W2584094173","https://openalex.org/W6623449936","https://openalex.org/W6667176412"],"related_works":["https://openalex.org/W2789662562","https://openalex.org/W4214735176","https://openalex.org/W2601542976","https://openalex.org/W2619968078","https://openalex.org/W2184476805","https://openalex.org/W2774143721","https://openalex.org/W2151687972","https://openalex.org/W4324145463","https://openalex.org/W4367312965","https://openalex.org/W2580743037"],"abstract_inverted_index":{"Memristor":[0],"is":[1,59],"considered":[2],"as":[3],"one":[4,88],"of":[5,13,75],"the":[6,10,14,60,76],"promising":[7],"solutions":[8],"to":[9],"fundamental":[11],"limitations":[12],"VLSI":[15],"systems.":[16],"Logic":[17],"implementation":[18,57,69,103],"with":[19,26,67,95],"memristor":[20,63],"device":[21],"by":[22,42],"considering":[23],"its":[24],"compatibility":[25],"CMOS":[27],"fabric":[28],"provides":[29],"a":[30,40,48],"new":[31],"vision":[32],"for":[33,62,92],"digital":[34],"logic":[35,65],"circuits.":[36],"This":[37,79],"work":[38],"presents":[39,100],"2":[41,43],"multiplier":[44],"cell":[45],"design":[46],"using":[47],"hybrid":[49],"CMOS-memristor":[50],"universal":[51,54],"gate.":[52],"The":[53],"gate":[55],"based":[56],"approach":[58,99],"extension":[61],"ratioed":[64],"(MRL)":[66],"lower":[68,102],"cost.":[70,104],"Simulation":[71],"results":[72],"confirm":[73],"functionality":[74],"proposed":[77],"circuit.":[78],"circuit":[80],"requires":[81],"16":[82],"memristors,":[83],"8":[84],"transistors":[85],"and":[86],"only":[87],"computational":[89],"time":[90],"step":[91],"multiplication.":[93],"Compared":[94],"previous":[96],"works,":[97],"this":[98],"considerably":[101]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":5},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":6},{"year":2021,"cited_by_count":5},{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1}],"updated_date":"2026-04-07T06:01:17.266235","created_date":"2025-10-10T00:00:00"}