{"id":"https://openalex.org/W2759343736","doi":"https://doi.org/10.1109/mwscas.2017.8053144","title":"Time-efficient and TSV-aware 3D gated clock tree synthesis based on self-tuning spectral clustering","display_name":"Time-efficient and TSV-aware 3D gated clock tree synthesis based on self-tuning spectral clustering","publication_year":2017,"publication_date":"2017-08-01","ids":{"openalex":"https://openalex.org/W2759343736","doi":"https://doi.org/10.1109/mwscas.2017.8053144","mag":"2759343736"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas.2017.8053144","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2017.8053144","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5102733732","display_name":"Fan Yang","orcid":null},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Fan Yang","raw_affiliation_strings":["Graduate School of Information, Production and System, Waseda University, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Information, Production and System, Waseda University, Japan","institution_ids":["https://openalex.org/I150744194"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036978288","display_name":"Minghao Lin","orcid":null},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Minghao Lin","raw_affiliation_strings":["Graduate School of Information, Production and System, Waseda University, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Information, Production and System, Waseda University, Japan","institution_ids":["https://openalex.org/I150744194"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5089205282","display_name":"Heming Sun","orcid":"https://orcid.org/0000-0001-5583-4895"},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Heming Sun","raw_affiliation_strings":["Graduate School of Information, Production and System, Waseda University, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Information, Production and System, Waseda University, Japan","institution_ids":["https://openalex.org/I150744194"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103496033","display_name":"Shinji Kimura","orcid":null},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Shinji Kimura","raw_affiliation_strings":["Graduate School of Information, Production and System, Waseda University, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Information, Production and System, Waseda University, Japan","institution_ids":["https://openalex.org/I150744194"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5102733732"],"corresponding_institution_ids":["https://openalex.org/I150744194"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.12458941,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":95},"biblio":{"volume":"31","issue":null,"first_page":"1200","last_page":"1203"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/tree-traversal","display_name":"Tree traversal","score":0.7642024755477905},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6899981498718262},{"id":"https://openalex.org/keywords/embedding","display_name":"Embedding","score":0.5744994282722473},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5142776370048523},{"id":"https://openalex.org/keywords/cluster-analysis","display_name":"Cluster analysis","score":0.5030481219291687},{"id":"https://openalex.org/keywords/tree","display_name":"Tree (set theory)","score":0.48244553804397583},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.46171805262565613},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.43165040016174316},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.42557308077812195},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2381104826927185},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1299571394920349},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.12533798813819885}],"concepts":[{"id":"https://openalex.org/C140745168","wikidata":"https://www.wikidata.org/wiki/Q1210082","display_name":"Tree traversal","level":2,"score":0.7642024755477905},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6899981498718262},{"id":"https://openalex.org/C41608201","wikidata":"https://www.wikidata.org/wiki/Q980509","display_name":"Embedding","level":2,"score":0.5744994282722473},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5142776370048523},{"id":"https://openalex.org/C73555534","wikidata":"https://www.wikidata.org/wiki/Q622825","display_name":"Cluster analysis","level":2,"score":0.5030481219291687},{"id":"https://openalex.org/C113174947","wikidata":"https://www.wikidata.org/wiki/Q2859736","display_name":"Tree (set theory)","level":2,"score":0.48244553804397583},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.46171805262565613},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.43165040016174316},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.42557308077812195},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2381104826927185},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1299571394920349},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.12533798813819885},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mwscas.2017.8053144","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2017.8053144","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1886215955","https://openalex.org/W1973183555","https://openalex.org/W1974610062","https://openalex.org/W1978169009","https://openalex.org/W2023981464","https://openalex.org/W2050088069","https://openalex.org/W2136047350","https://openalex.org/W2149417654","https://openalex.org/W2152322845","https://openalex.org/W2550594528","https://openalex.org/W3000662989","https://openalex.org/W6729691334"],"related_works":["https://openalex.org/W170547082","https://openalex.org/W2136735429","https://openalex.org/W4229950834","https://openalex.org/W3107197685","https://openalex.org/W2908418870","https://openalex.org/W48124421","https://openalex.org/W272774291","https://openalex.org/W2604902477","https://openalex.org/W3202117991","https://openalex.org/W1972574144"],"abstract_inverted_index":{"3D":[0,110],"gated":[1],"clock":[2,13,25,56],"tree":[3,26,57],"synthesis":[4],"(CTS)":[5],"mainly":[6],"consists":[7],"of":[8,80],"three":[9],"steps:":[10],"1)":[11],"abstract":[12],"topology":[14,58],"generation;":[15],"2)":[16],"layer":[17,69,79],"embedding":[18,70,78],"for":[19,75],"minimal":[20,84],"TSV":[21,85,114],"allocation":[22],"and":[23,30,96,102],"3)":[24],"routing":[27],"with":[28,45,60,83,107],"gate":[29],"buffer":[31],"insertion.":[32],"In":[33,63],"this":[34],"paper,":[35],"a":[36,65],"self-tuning":[37],"spectral":[38],"clustering":[39],"based":[40,68],"nearest-neighbor":[41],"selection":[42],"(SSC-NNS)":[43],"algorithm":[44],"parallel":[46],"structure":[47],"is":[48,73,116],"proposed":[49,92],"to":[50],"achieve":[51],"high":[52],"time":[53],"efficiency":[54],"in":[55],"generation,":[59],"reduced":[61,118],"runtime.":[62],"addition,":[64],"postorder":[66],"traversal":[67],"(PTLE)":[71],"strategy":[72],"adopted":[74],"determining":[76],"the":[77,91,108,113],"internal":[81],"nodes":[82],"usages.":[86],"Experimental":[87],"results":[88],"show":[89],"that":[90],"method":[93],"achieves":[94],"32%":[95],"82%":[97],"runtime":[98],"reduction":[99],"on":[100,121],"ISPD2009":[101,122],"IBM":[103],"benchmarks":[104],"respectively":[105],"compared":[106],"state-of-the-art":[109],"work.":[111],"Besides,":[112],"count":[115],"also":[117],"by":[119],"46%":[120],"benchmarks.":[123]},"counts_by_year":[{"year":2025,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
