{"id":"https://openalex.org/W2759441830","doi":"https://doi.org/10.1109/mwscas.2017.8053142","title":"A comparison of quasi-delay-insensitive asynchronous adder designs corresponding to return-to-zero and return-to-one handshaking","display_name":"A comparison of quasi-delay-insensitive asynchronous adder designs corresponding to return-to-zero and return-to-one handshaking","publication_year":2017,"publication_date":"2017-08-01","ids":{"openalex":"https://openalex.org/W2759441830","doi":"https://doi.org/10.1109/mwscas.2017.8053142","mag":"2759441830"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas.2017.8053142","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2017.8053142","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5008761321","display_name":"Padmanabhan Balasubramanian","orcid":"https://orcid.org/0000-0001-9412-4773"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":true,"raw_author_name":"P. Balasubramanian","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5036110351","display_name":"Cuong Dang","orcid":"https://orcid.org/0000-0001-6183-4082"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"C. Dang","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5008761321"],"corresponding_institution_ids":["https://openalex.org/I172675005"],"apc_list":null,"apc_paid":null,"fwci":2.0068,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":{"value":0.87616613,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":"10","issue":null,"first_page":"1192","last_page":"1195"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/handshaking","display_name":"Handshaking","score":0.8028973340988159},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.657905101776123},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.6425516605377197},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.6397920846939087},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.535534679889679},{"id":"https://openalex.org/keywords/handshake","display_name":"Handshake","score":0.471734881401062},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.43253618478775024},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.4277428686618805},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3920033574104309},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.25663164258003235},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.1423603892326355},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10016846656799316}],"concepts":[{"id":"https://openalex.org/C58861099","wikidata":"https://www.wikidata.org/wiki/Q548838","display_name":"Handshaking","level":2,"score":0.8028973340988159},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.657905101776123},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.6425516605377197},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.6397920846939087},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.535534679889679},{"id":"https://openalex.org/C2778000800","wikidata":"https://www.wikidata.org/wiki/Q830043","display_name":"Handshake","level":3,"score":0.471734881401062},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.43253618478775024},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.4277428686618805},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3920033574104309},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.25663164258003235},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1423603892326355},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10016846656799316},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mwscas.2017.8053142","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2017.8053142","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W51000313","https://openalex.org/W204599048","https://openalex.org/W1522009072","https://openalex.org/W1812041132","https://openalex.org/W1926711212","https://openalex.org/W1980852150","https://openalex.org/W1999082644","https://openalex.org/W2000938657","https://openalex.org/W2052771421","https://openalex.org/W2059456074","https://openalex.org/W2062939399","https://openalex.org/W2082494481","https://openalex.org/W2105621006","https://openalex.org/W2134829921","https://openalex.org/W2142118396","https://openalex.org/W2152229138","https://openalex.org/W2338325078","https://openalex.org/W2487142227","https://openalex.org/W2540271382","https://openalex.org/W3102709200","https://openalex.org/W3103253484","https://openalex.org/W6602063647","https://openalex.org/W6608306146","https://openalex.org/W6631409759"],"related_works":["https://openalex.org/W2347296673","https://openalex.org/W2521973011","https://openalex.org/W2036690923","https://openalex.org/W2066480039","https://openalex.org/W2061563403","https://openalex.org/W2019002109","https://openalex.org/W3163080401","https://openalex.org/W2576660463","https://openalex.org/W4388007616","https://openalex.org/W344978372"],"abstract_inverted_index":{"This":[0],"paper":[1],"makes":[2],"a":[3,16,42,58],"comparison":[4],"between":[5],"various":[6],"quasi-delay-insensitive":[7],"(QDI)":[8],"asynchronous":[9],"ripple":[10],"carry":[11],"adders":[12],"(RCAs)":[13],"realized":[14],"using":[15,57],"delay-insensitive":[17],"dual-rail":[18],"code":[19],"which":[20,54,70,84],"correspond":[21,40,71,85],"to":[22,41,72,79,86],"4-phase":[23,27],"return-to-zero":[24],"(RTZ)":[25],"and":[26,39,52,97],"return-to-one":[28],"(RTO)":[29],"handshaking.":[30],"The":[31,62],"QDI":[32,68,81],"RCAs":[33,69],"considered":[34],"are":[35,55,76],"32-bits":[36],"in":[37,90],"size":[38],"variety":[43],"of":[44,92],"timing":[45],"regimes":[46],"viz.":[47],"strong-indication,":[48],"weak-indication,":[49],"early":[50],"output,":[51],"relative-timed,":[53],"implemented":[56],"32/28nm":[59],"CMOS":[60],"process.":[61],"extensive":[63],"comparisons":[64],"show":[65],"that,":[66],"overall,":[67],"the":[73,87],"RTO":[74],"protocol":[75,89],"optimized":[77],"compared":[78],"their":[80],"RCA":[82],"counterparts":[83],"RTZ":[88],"terms":[91],"area,":[93],"power":[94],"dissipation,":[95],"latency,":[96],"cycle":[98],"time.":[99]},"counts_by_year":[{"year":2020,"cited_by_count":3},{"year":2019,"cited_by_count":5},{"year":2018,"cited_by_count":5},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}