{"id":"https://openalex.org/W2759835600","doi":"https://doi.org/10.1109/mwscas.2017.8053128","title":"Improving the performance of all-digital transmitter based on parallel delta-sigma modulators through propagation of state registers","display_name":"Improving the performance of all-digital transmitter based on parallel delta-sigma modulators through propagation of state registers","publication_year":2017,"publication_date":"2017-08-01","ids":{"openalex":"https://openalex.org/W2759835600","doi":"https://doi.org/10.1109/mwscas.2017.8053128","mag":"2759835600"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas.2017.8053128","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2017.8053128","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5050281072","display_name":"Daniel C. Dinis","orcid":"https://orcid.org/0000-0003-2471-4545"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Daniel C. Dinis","raw_affiliation_strings":["Dpartamento de Electr\u00f3nica, Universit\u00e1rio de Santiago, Aveiro, Portugal"],"affiliations":[{"raw_affiliation_string":"Dpartamento de Electr\u00f3nica, Universit\u00e1rio de Santiago, Aveiro, Portugal","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070624065","display_name":"Rui F. Cordeiro","orcid":"https://orcid.org/0000-0002-3384-2023"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Rui F. Cordeiro","raw_affiliation_strings":["Dpartamento de Electr\u00f3nica, Universit\u00e1rio de Santiago, Aveiro, Portugal"],"affiliations":[{"raw_affiliation_string":"Dpartamento de Electr\u00f3nica, Universit\u00e1rio de Santiago, Aveiro, Portugal","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087676170","display_name":"Arnaldo S. R. Oliveira","orcid":"https://orcid.org/0000-0002-8759-3456"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Arnaldo S. R. Oliveira","raw_affiliation_strings":["Dpartamento de Electr\u00f3nica, Universit\u00e1rio de Santiago, Aveiro, Portugal"],"affiliations":[{"raw_affiliation_string":"Dpartamento de Electr\u00f3nica, Universit\u00e1rio de Santiago, Aveiro, Portugal","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082374568","display_name":"Jos\u00e9 Vieira","orcid":"https://orcid.org/0000-0002-4356-4522"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Jose Vieira","raw_affiliation_strings":["Dpartamento de Electr\u00f3nica, Universit\u00e1rio de Santiago, Aveiro, Portugal"],"affiliations":[{"raw_affiliation_string":"Dpartamento de Electr\u00f3nica, Universit\u00e1rio de Santiago, Aveiro, Portugal","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5010021763","display_name":"Tomas O. Silva","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Tomas O. Silva","raw_affiliation_strings":["Dpartamento de Electr\u00f3nica, Universit\u00e1rio de Santiago, Aveiro, Portugal"],"affiliations":[{"raw_affiliation_string":"Dpartamento de Electr\u00f3nica, Universit\u00e1rio de Santiago, Aveiro, Portugal","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5050281072"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.0197,"has_fulltext":false,"cited_by_count":18,"citation_normalized_percentile":{"value":0.74991038,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"1133","last_page":"1137"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/transmitter","display_name":"Transmitter","score":0.8240278363227844},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7695763111114502},{"id":"https://openalex.org/keywords/delta-sigma-modulation","display_name":"Delta-sigma modulation","score":0.744386613368988},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7237122058868408},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.6420825123786926},{"id":"https://openalex.org/keywords/wideband","display_name":"Wideband","score":0.568916380405426},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.46483609080314636},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.44785645604133606},{"id":"https://openalex.org/keywords/state","display_name":"State (computer science)","score":0.43997079133987427},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.42790675163269043},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3240150213241577},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.19856485724449158},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.1792830228805542},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1717599630355835},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.16911983489990234},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.07010847330093384}],"concepts":[{"id":"https://openalex.org/C47798520","wikidata":"https://www.wikidata.org/wiki/Q190157","display_name":"Transmitter","level":3,"score":0.8240278363227844},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7695763111114502},{"id":"https://openalex.org/C68754193","wikidata":"https://www.wikidata.org/wiki/Q1184820","display_name":"Delta-sigma modulation","level":3,"score":0.744386613368988},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7237122058868408},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.6420825123786926},{"id":"https://openalex.org/C2780202535","wikidata":"https://www.wikidata.org/wiki/Q4524457","display_name":"Wideband","level":2,"score":0.568916380405426},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.46483609080314636},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.44785645604133606},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.43997079133987427},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.42790675163269043},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3240150213241577},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.19856485724449158},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.1792830228805542},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1717599630355835},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.16911983489990234},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.07010847330093384},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mwscas.2017.8053128","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2017.8053128","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.44999998807907104}],"awards":[],"funders":[{"id":"https://openalex.org/F4320334779","display_name":"Funda\u00e7\u00e3o para a Ci\u00eancia e a Tecnologia","ror":"https://ror.org/00snfqn58"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1604910465","https://openalex.org/W2037592225","https://openalex.org/W2080332318","https://openalex.org/W2106239808","https://openalex.org/W2508250407"],"related_works":["https://openalex.org/W2355663289","https://openalex.org/W2106913410","https://openalex.org/W4380372336","https://openalex.org/W2354248671","https://openalex.org/W2359134391","https://openalex.org/W2594116857","https://openalex.org/W2947628004","https://openalex.org/W2935229758","https://openalex.org/W1978532702","https://openalex.org/W2387385112"],"abstract_inverted_index":{"In":[0],"this":[1],"paper":[2],"it":[3],"will":[4],"be":[5,64],"shown":[6],"that":[7,57],"propagating":[8],"specific":[9],"state":[10],"registers":[11],"in":[12,23,35],"a":[13,20,70],"fully":[14],"parallel":[15],"Delta-Sigma":[16],"Architecture":[17],"can":[18,63],"have":[19],"profound":[21],"impact":[22],"enhancing":[24],"the":[25,51],"performance":[26],"of":[27,30,37],"these":[28],"type":[29],"modulators":[31,62],"without":[32],"stringent":[33],"requirements":[34],"terms":[36],"latency":[38],"and":[39,47,54,60,68],"resources":[40,72],"usage.":[41,73],"An":[42],"FPGA-based":[43],"transmitter":[44],"was":[45],"implemented":[46,65],"designed":[48],"to":[49,55],"validate":[50],"proposed":[52],"architecture,":[53],"demonstrate":[56],"flexible,":[58],"high-speed":[59],"wideband":[61],"with":[66,69],"low-complexity":[67],"low":[71]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":5},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}