{"id":"https://openalex.org/W2759816080","doi":"https://doi.org/10.1109/mwscas.2017.8053097","title":"High speed digital ELD compensation with hybrid thermometer coding in CT \u0394\u03a3 modulators","display_name":"High speed digital ELD compensation with hybrid thermometer coding in CT \u0394\u03a3 modulators","publication_year":2017,"publication_date":"2017-08-01","ids":{"openalex":"https://openalex.org/W2759816080","doi":"https://doi.org/10.1109/mwscas.2017.8053097","mag":"2759816080"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas.2017.8053097","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2017.8053097","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5064532270","display_name":"Hang Hu","orcid":"https://orcid.org/0000-0002-1211-9864"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Hang Hu","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, P. R. China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, P. R. China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072097077","display_name":"Zemin Feng","orcid":"https://orcid.org/0000-0003-3815-5596"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zemin Feng","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, P. R. China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, P. R. China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051205321","display_name":"Chixiao Chen","orcid":"https://orcid.org/0000-0002-5980-4236"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Chixiao Chen","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, P. R. China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, P. R. China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025053306","display_name":"Fan Ye","orcid":"https://orcid.org/0000-0002-1089-1498"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Fan Ye","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, P. R. China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, P. R. China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5016448886","display_name":"Junyan Ren","orcid":"https://orcid.org/0000-0002-7799-6251"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Junyan Ren","raw_affiliation_strings":["State Key Laboratory of ASIC and System, Fudan University, Shanghai, P. R. China"],"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC and System, Fudan University, Shanghai, P. R. China","institution_ids":["https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5064532270"],"corresponding_institution_ids":["https://openalex.org/I24943067"],"apc_list":null,"apc_paid":null,"fwci":0.2549,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.55369025,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1009","last_page":"1012"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9952999949455261,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/compensation","display_name":"Compensation (psychology)","score":0.7509036064147949},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5997775197029114},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.57976895570755},{"id":"https://openalex.org/keywords/coding","display_name":"Coding (social sciences)","score":0.5649195313453674},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5353138446807861},{"id":"https://openalex.org/keywords/feedback-loop","display_name":"Feedback loop","score":0.48401519656181335},{"id":"https://openalex.org/keywords/delta-sigma-modulation","display_name":"Delta-sigma modulation","score":0.4572162330150604},{"id":"https://openalex.org/keywords/baseband","display_name":"Baseband","score":0.4335963726043701},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.41724133491516113},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22914248704910278}],"concepts":[{"id":"https://openalex.org/C2780023022","wikidata":"https://www.wikidata.org/wiki/Q1338171","display_name":"Compensation (psychology)","level":2,"score":0.7509036064147949},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5997775197029114},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.57976895570755},{"id":"https://openalex.org/C179518139","wikidata":"https://www.wikidata.org/wiki/Q5140297","display_name":"Coding (social sciences)","level":2,"score":0.5649195313453674},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5353138446807861},{"id":"https://openalex.org/C186886427","wikidata":"https://www.wikidata.org/wiki/Q5441213","display_name":"Feedback loop","level":2,"score":0.48401519656181335},{"id":"https://openalex.org/C68754193","wikidata":"https://www.wikidata.org/wiki/Q1184820","display_name":"Delta-sigma modulation","level":3,"score":0.4572162330150604},{"id":"https://openalex.org/C65165936","wikidata":"https://www.wikidata.org/wiki/Q575784","display_name":"Baseband","level":3,"score":0.4335963726043701},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.41724133491516113},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22914248704910278},{"id":"https://openalex.org/C15744967","wikidata":"https://www.wikidata.org/wiki/Q9418","display_name":"Psychology","level":0,"score":0.0},{"id":"https://openalex.org/C11171543","wikidata":"https://www.wikidata.org/wiki/Q41630","display_name":"Psychoanalysis","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mwscas.2017.8053097","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2017.8053097","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1996014834","https://openalex.org/W2107964070","https://openalex.org/W2118068838","https://openalex.org/W2151133875","https://openalex.org/W2292998224"],"related_works":["https://openalex.org/W2204547643","https://openalex.org/W1497578837","https://openalex.org/W4293208944","https://openalex.org/W4294892273","https://openalex.org/W2355697382","https://openalex.org/W2296733454","https://openalex.org/W2070707130","https://openalex.org/W2109547927","https://openalex.org/W2055066428","https://openalex.org/W1580340080"],"abstract_inverted_index":{"In":[0,19],"this":[1,20,60],"paper,":[2],"a":[3,67,72,87],"high":[4,21,73],"speed":[5,22],"digital":[6,57,77],"excess":[7],"loop":[8],"delay":[9],"(ELD)":[10],"compensation":[11,38,65,79],"scheme":[12,61,80],"with":[13,45,66],"hybrid":[14],"thermometer":[15],"coding":[16],"is":[17,32,52],"proposed.":[18],"compensation,":[23],"the":[24,28,35,41,46,49,82],"time":[25],"constraint":[26],"of":[27,89],"DAC":[29],"feedback":[30],"route":[31],"shifted":[33],"to":[34,43,55],"one":[36],"clock":[37],"path.":[39],"Also,":[40],"method":[42],"deal":[44],"signal":[47],"overflows":[48],"quantizer's":[50],"range":[51],"analyzed.":[53],"Compared":[54],"other":[56],"ELD":[58,78],"compensations,":[59],"features":[62],"an":[63],"efficient":[64],"low":[68],"hardware":[69],"cost":[70],"and":[71,81],"operation":[74],"frequency.":[75],"The":[76],"algorithm":[83],"were":[84],"verified":[85],"in":[86,94],"design":[88],"3-0":[90],"MASH":[91],"delta-sigma":[92],"modulator":[93],"TSMC":[95],"65nm":[96],"LP":[97],"CMOS":[98],"process.":[99]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
