{"id":"https://openalex.org/W2760700235","doi":"https://doi.org/10.1109/mwscas.2017.8053068","title":"(Invited) Software-guided greybox design methodology with integrated power and clock management","display_name":"(Invited) Software-guided greybox design methodology with integrated power and clock management","publication_year":2017,"publication_date":"2017-08-01","ids":{"openalex":"https://openalex.org/W2760700235","doi":"https://doi.org/10.1109/mwscas.2017.8053068","mag":"2760700235"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas.2017.8053068","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2017.8053068","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5088551028","display_name":"Tianyu Jia","orcid":"https://orcid.org/0000-0002-4570-4613"},"institutions":[{"id":"https://openalex.org/I111979921","display_name":"Northwestern University","ror":"https://ror.org/000e0be47","country_code":"US","type":"education","lineage":["https://openalex.org/I111979921"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tianyu Jia","raw_affiliation_strings":["Department of Electrical Engineering and Computer Science, Northwestern University, Evanston, IL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering and Computer Science, Northwestern University, Evanston, IL, USA","institution_ids":["https://openalex.org/I111979921"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5065095463","display_name":"Yuanbo Fan","orcid":null},"institutions":[{"id":"https://openalex.org/I111979921","display_name":"Northwestern University","ror":"https://ror.org/000e0be47","country_code":"US","type":"education","lineage":["https://openalex.org/I111979921"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yuanbo Fan","raw_affiliation_strings":["Department of Electrical Engineering and Computer Science, Northwestern University, Evanston, IL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering and Computer Science, Northwestern University, Evanston, IL, USA","institution_ids":["https://openalex.org/I111979921"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068821873","display_name":"Russ Joseph","orcid":"https://orcid.org/0000-0001-6349-1888"},"institutions":[{"id":"https://openalex.org/I111979921","display_name":"Northwestern University","ror":"https://ror.org/000e0be47","country_code":"US","type":"education","lineage":["https://openalex.org/I111979921"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Russ Joseph","raw_affiliation_strings":["Department of Electrical Engineering and Computer Science, Northwestern University, Evanston, IL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering and Computer Science, Northwestern University, Evanston, IL, USA","institution_ids":["https://openalex.org/I111979921"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5005991726","display_name":"Jie Gu","orcid":"https://orcid.org/0000-0003-2912-7294"},"institutions":[{"id":"https://openalex.org/I111979921","display_name":"Northwestern University","ror":"https://ror.org/000e0be47","country_code":"US","type":"education","lineage":["https://openalex.org/I111979921"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jie Gu","raw_affiliation_strings":["Department of Electrical Engineering and Computer Science, Northwestern University, Evanston, IL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering and Computer Science, Northwestern University, Evanston, IL, USA","institution_ids":["https://openalex.org/I111979921"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I111979921"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.10496991,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"34","issue":null,"first_page":"894","last_page":"897"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6970587968826294},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.6423305869102478},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.604443371295929},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4935406446456909},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4890492856502533},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.47269299626350403},{"id":"https://openalex.org/keywords/design-methods","display_name":"Design methods","score":0.4543915390968323},{"id":"https://openalex.org/keywords/microarchitecture","display_name":"Microarchitecture","score":0.4454367160797119},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.4322204291820526},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.4298953711986542},{"id":"https://openalex.org/keywords/bridge","display_name":"Bridge (graph theory)","score":0.4198925495147705},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.34695154428482056},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17940610647201538},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.10983648896217346}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6970587968826294},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.6423305869102478},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.604443371295929},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4935406446456909},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4890492856502533},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.47269299626350403},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.4543915390968323},{"id":"https://openalex.org/C107598950","wikidata":"https://www.wikidata.org/wiki/Q259864","display_name":"Microarchitecture","level":2,"score":0.4454367160797119},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.4322204291820526},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.4298953711986542},{"id":"https://openalex.org/C100776233","wikidata":"https://www.wikidata.org/wiki/Q2532492","display_name":"Bridge (graph theory)","level":2,"score":0.4198925495147705},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.34695154428482056},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17940610647201538},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.10983648896217346},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C71924100","wikidata":"https://www.wikidata.org/wiki/Q11190","display_name":"Medicine","level":0,"score":0.0},{"id":"https://openalex.org/C126322002","wikidata":"https://www.wikidata.org/wiki/Q11180","display_name":"Internal medicine","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mwscas.2017.8053068","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2017.8053068","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.6600000262260437,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1991670063","https://openalex.org/W1996802375","https://openalex.org/W2036853599","https://openalex.org/W2059774354","https://openalex.org/W2112008043","https://openalex.org/W2160398557","https://openalex.org/W2171461313","https://openalex.org/W2178304595","https://openalex.org/W2217616241","https://openalex.org/W2404136550","https://openalex.org/W2625870498","https://openalex.org/W4242565052","https://openalex.org/W4249633267"],"related_works":["https://openalex.org/W2366617252","https://openalex.org/W2078506771","https://openalex.org/W2126983197","https://openalex.org/W1965232212","https://openalex.org/W1987513258","https://openalex.org/W2146942794","https://openalex.org/W1963851171","https://openalex.org/W2151657833","https://openalex.org/W2148163917","https://openalex.org/W2109207559"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3],"propose":[4],"a":[5,40,90],"cross-layer":[6,61],"integrated":[7,42],"microprocessor":[8],"design":[9,18,43,57,78,112],"methodology":[10,79],"where":[11],"instructions":[12],"in":[13,37,89],"software":[14,55,85],"programs":[15],"drive":[16],"the":[17,21,30,38,68,82,110],"down":[19],"to":[20],"gate":[22],"level":[23],"netlists.":[24],"Based":[25],"on":[26,104],"in-depth":[27],"exploration":[28],"of":[29,34],"dynamic":[31],"timing":[32],"behavior":[33],"each":[35],"instruction":[36],"program,":[39],"fully":[41],"approach":[44],"is":[45,64],"proposed":[46,77,111],"with":[47],"ultra-dynamic":[48],"clock":[49],"and":[50,54,74,86,106],"power":[51,107],"management":[52],"circuits":[53],"driven":[56],"optimization":[58],"approach.":[59],"A":[60],"simulation":[62],"environment":[63],"also":[65],"introduced":[66],"enabling":[67],"collaborative":[69],"co-design":[70],"among":[71],"compiler,":[72],"architecture":[73],"circuits.":[75],"The":[76],"helps":[80],"bridge":[81],"gap":[83],"between":[84],"hardware":[87],"development":[88,92],"conventional":[91],"cycle.":[93],"Our":[94],"test":[95],"vehicle":[96],"using":[97,109],"ARM":[98],"based":[99],"processor":[100],"demonstrates":[101],"substantial":[102],"improvement":[103],"speed":[105],"efficiency":[108],"methodology.":[113]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}