{"id":"https://openalex.org/W2758721118","doi":"https://doi.org/10.1109/mwscas.2017.8053019","title":"Area efficient soft error tolerant RISC pipeline: Leveraging data encoding and inherent ALU redundancy","display_name":"Area efficient soft error tolerant RISC pipeline: Leveraging data encoding and inherent ALU redundancy","publication_year":2017,"publication_date":"2017-08-01","ids":{"openalex":"https://openalex.org/W2758721118","doi":"https://doi.org/10.1109/mwscas.2017.8053019","mag":"2758721118"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas.2017.8053019","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2017.8053019","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5034599612","display_name":"Syed Rafay Hasan","orcid":"https://orcid.org/0000-0003-0183-8086"},"institutions":[{"id":"https://openalex.org/I63920570","display_name":"Tennessee Technological University","ror":"https://ror.org/05drmrq39","country_code":"US","type":"education","lineage":["https://openalex.org/I63920570"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Syed Rafay Hasan","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Tennessee Tech University, Cookeville, TN, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Tennessee Tech University, Cookeville, TN, USA","institution_ids":["https://openalex.org/I63920570"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5014912655","display_name":"Phani Balaji Swamy Tangellapalli","orcid":null},"institutions":[{"id":"https://openalex.org/I63920570","display_name":"Tennessee Technological University","ror":"https://ror.org/05drmrq39","country_code":"US","type":"education","lineage":["https://openalex.org/I63920570"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Phani Tangellapalli","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Tennessee Tech University, Cookeville, TN, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Tennessee Tech University, Cookeville, TN, USA","institution_ids":["https://openalex.org/I63920570"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5034599612"],"corresponding_institution_ids":["https://openalex.org/I63920570"],"apc_list":null,"apc_paid":null,"fwci":0.2867,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.59830466,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"23","issue":null,"first_page":"699","last_page":"702"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8350452184677124},{"id":"https://openalex.org/keywords/operand","display_name":"Operand","score":0.6994898319244385},{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.6375858783721924},{"id":"https://openalex.org/keywords/reduced-instruction-set-computing","display_name":"Reduced instruction set computing","score":0.6154161095619202},{"id":"https://openalex.org/keywords/soft-error","display_name":"Soft error","score":0.6145087480545044},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.5750110745429993},{"id":"https://openalex.org/keywords/error-detection-and-correction","display_name":"Error detection and correction","score":0.5502826571464539},{"id":"https://openalex.org/keywords/stratix","display_name":"Stratix","score":0.5298488140106201},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5188878178596497},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.50920170545578},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5022890567779541},{"id":"https://openalex.org/keywords/encoding","display_name":"Encoding (memory)","score":0.48716017603874207},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3851422667503357},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.332729309797287},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.24673518538475037},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.09606382250785828},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.09341943264007568},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.0871075987815857}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8350452184677124},{"id":"https://openalex.org/C55526617","wikidata":"https://www.wikidata.org/wiki/Q719375","display_name":"Operand","level":2,"score":0.6994898319244385},{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.6375858783721924},{"id":"https://openalex.org/C126298526","wikidata":"https://www.wikidata.org/wiki/Q189376","display_name":"Reduced instruction set computing","level":3,"score":0.6154161095619202},{"id":"https://openalex.org/C154474529","wikidata":"https://www.wikidata.org/wiki/Q1658917","display_name":"Soft error","level":2,"score":0.6145087480545044},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.5750110745429993},{"id":"https://openalex.org/C103088060","wikidata":"https://www.wikidata.org/wiki/Q1062839","display_name":"Error detection and correction","level":2,"score":0.5502826571464539},{"id":"https://openalex.org/C2776277307","wikidata":"https://www.wikidata.org/wiki/Q22074755","display_name":"Stratix","level":3,"score":0.5298488140106201},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5188878178596497},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.50920170545578},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5022890567779541},{"id":"https://openalex.org/C125411270","wikidata":"https://www.wikidata.org/wiki/Q18653","display_name":"Encoding (memory)","level":2,"score":0.48716017603874207},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3851422667503357},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.332729309797287},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.24673518538475037},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.09606382250785828},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.09341943264007568},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0871075987815857},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mwscas.2017.8053019","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2017.8053019","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W160422864","https://openalex.org/W1984630859","https://openalex.org/W1997201851","https://openalex.org/W1999684621","https://openalex.org/W2009523258","https://openalex.org/W2102421762","https://openalex.org/W2105956212","https://openalex.org/W2126183865","https://openalex.org/W2127957019","https://openalex.org/W2167135469","https://openalex.org/W2169213530","https://openalex.org/W2178304595","https://openalex.org/W4285719527"],"related_works":["https://openalex.org/W4200457651","https://openalex.org/W4389476319","https://openalex.org/W4241438378","https://openalex.org/W2538644970","https://openalex.org/W2111003880","https://openalex.org/W4376881175","https://openalex.org/W4310584696","https://openalex.org/W4237840813","https://openalex.org/W4364295250","https://openalex.org/W2062172248"],"abstract_inverted_index":{"This":[0],"paper":[1],"proposes":[2],"novel":[3],"soft":[4,80,136],"error":[5,81,137],"detection":[6],"and":[7,134],"mitigation":[8],"technique":[9,121],"in":[10,30,37,57,95,139],"reduced":[11],"instruction":[12],"set":[13],"computer":[14],"(RISC)":[15],"based":[16,93],"pipeline":[17,38],"processors.":[18],"We":[19],"leveraged":[20],"the":[21,44,53,75,106],"data":[22,60,98],"encoding":[23,99],"techniques":[24,133],"(re-computing":[25],"with":[26,32,59,97,143],"rotated":[27],"operands":[28],"(RERO))":[29],"conjunction":[31,58,96],"back":[33],"pressure":[34],"controlling":[35],"mechanism":[36],"architecture.":[39],"In":[40],"order":[41],"to":[42,48,79,112,124,130],"alleviate":[43],"performance":[45],"degradation":[46],"due":[47],"potential":[49],"stalling,":[50],"we":[51],"exploited":[52],"inherent":[54],"ALU":[55],"redundancy":[56],"encoding.":[61],"Synthesis":[62],"results":[63],"on":[64],"Stratix":[65],"II":[66],"FPGA":[67],"from":[68],"Altera":[69],"suggested":[70],"that":[71],"if":[72,105],"5%":[73],"of":[74,115],"instructions":[76],"are":[77],"subject":[78],"then":[82],"for":[83],"2.25":[84],"additional":[85,116],"stall":[86],"cycles":[87],"(on":[88],"average)":[89],"our":[90,120],"proposed":[91],"ALU-redundancy":[92],"solution":[94],"provides":[100,135],"better":[101],"execution":[102],"time":[103,109],"even":[104],"clock":[107],"cycle":[108],"increases":[110],"up":[111,123],"11%":[113],"because":[114],"hardware.":[117],"Area":[118],"wise":[119],"requires":[122],"3":[125],"times":[126],"lesser":[127],"area":[128],"compared":[129],"other":[131],"contemporary":[132],"tolerance":[138],"combinational":[140],"blocks":[141],"along":[142],"intermediate":[144],"registers.":[145]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
