{"id":"https://openalex.org/W2758120191","doi":"https://doi.org/10.1109/mwscas.2017.8053006","title":"Statistical accuracy analysis of complex floating point multipliers","display_name":"Statistical accuracy analysis of complex floating point multipliers","publication_year":2017,"publication_date":"2017-08-01","ids":{"openalex":"https://openalex.org/W2758120191","doi":"https://doi.org/10.1109/mwscas.2017.8053006","mag":"2758120191"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas.2017.8053006","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2017.8053006","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5056788021","display_name":"Violeta Reyes-Rodriguez","orcid":null},"institutions":[{"id":"https://openalex.org/I60388903","display_name":"University of Puerto Rico-Mayaguez","ror":"https://ror.org/00wek6x04","country_code":"PR","type":"education","lineage":["https://openalex.org/I200399037","https://openalex.org/I60388903"]}],"countries":["PR"],"is_corresponding":true,"raw_author_name":"Violeta Reyes-Rodriguez","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Puerto Rico at Mayag\u00fcez, Mayag\u00fcez, Puerto Rico"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Puerto Rico at Mayag\u00fcez, Mayag\u00fcez, Puerto Rico","institution_ids":["https://openalex.org/I60388903"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100599698","display_name":"Manuel Jim\u00e9nez","orcid":"https://orcid.org/0000-0003-0497-1480"},"institutions":[{"id":"https://openalex.org/I60388903","display_name":"University of Puerto Rico-Mayaguez","ror":"https://ror.org/00wek6x04","country_code":"PR","type":"education","lineage":["https://openalex.org/I200399037","https://openalex.org/I60388903"]}],"countries":["PR"],"is_corresponding":false,"raw_author_name":"Manuel Jimenez","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Puerto Rico at Mayag\u00fcez, Mayag\u00fcez, Puerto Rico"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Puerto Rico at Mayag\u00fcez, Mayag\u00fcez, Puerto Rico","institution_ids":["https://openalex.org/I60388903"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050299894","display_name":"Keisha Y. Castillo-Torres","orcid":"https://orcid.org/0000-0002-5524-1931"},"institutions":[{"id":"https://openalex.org/I60388903","display_name":"University of Puerto Rico-Mayaguez","ror":"https://ror.org/00wek6x04","country_code":"PR","type":"education","lineage":["https://openalex.org/I200399037","https://openalex.org/I60388903"]}],"countries":["PR"],"is_corresponding":false,"raw_author_name":"Keisha Castillo-Torres","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Puerto Rico at Mayag\u00fcez, Mayag\u00fcez, Puerto Rico"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Puerto Rico at Mayag\u00fcez, Mayag\u00fcez, Puerto Rico","institution_ids":["https://openalex.org/I60388903"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059354205","display_name":"Sylmarie D\u00e1vila-Montero","orcid":"https://orcid.org/0000-0001-8387-0535"},"institutions":[{"id":"https://openalex.org/I60388903","display_name":"University of Puerto Rico-Mayaguez","ror":"https://ror.org/00wek6x04","country_code":"PR","type":"education","lineage":["https://openalex.org/I200399037","https://openalex.org/I60388903"]}],"countries":["PR"],"is_corresponding":false,"raw_author_name":"Sylmarie Davila-Montero","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Puerto Rico at Mayag\u00fcez, Mayag\u00fcez, Puerto Rico"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Puerto Rico at Mayag\u00fcez, Mayag\u00fcez, Puerto Rico","institution_ids":["https://openalex.org/I60388903"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101793593","display_name":"Domingo Rodr\u0131\u0301guez","orcid":"https://orcid.org/0000-0003-0493-5156"},"institutions":[{"id":"https://openalex.org/I60388903","display_name":"University of Puerto Rico-Mayaguez","ror":"https://ror.org/00wek6x04","country_code":"PR","type":"education","lineage":["https://openalex.org/I200399037","https://openalex.org/I60388903"]}],"countries":["PR"],"is_corresponding":false,"raw_author_name":"Domingo Rodriguez","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Puerto Rico at Mayag\u00fcez, Mayag\u00fcez, Puerto Rico"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Puerto Rico at Mayag\u00fcez, Mayag\u00fcez, Puerto Rico","institution_ids":["https://openalex.org/I60388903"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5056788021"],"corresponding_institution_ids":["https://openalex.org/I60388903"],"apc_list":null,"apc_paid":null,"fwci":0.2271,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.56402264,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"647","last_page":"650"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7762584090232849},{"id":"https://openalex.org/keywords/scalar-multiplication","display_name":"Scalar multiplication","score":0.727065920829773},{"id":"https://openalex.org/keywords/operand","display_name":"Operand","score":0.7147303223609924},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7141189575195312},{"id":"https://openalex.org/keywords/multiplication","display_name":"Multiplication (music)","score":0.6487643122673035},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.6196213960647583},{"id":"https://openalex.org/keywords/floating-point","display_name":"Floating point","score":0.5449070930480957},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.5141737461090088},{"id":"https://openalex.org/keywords/single-precision-floating-point-format","display_name":"Single-precision floating-point format","score":0.47152289748191833},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4283389449119568},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3870163857936859},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.36903679370880127},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.3514425754547119},{"id":"https://openalex.org/keywords/scalar","display_name":"Scalar (mathematics)","score":0.33281463384628296},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3232544958591461},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3214123845100403},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.13001799583435059}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7762584090232849},{"id":"https://openalex.org/C171182647","wikidata":"https://www.wikidata.org/wiki/Q126736","display_name":"Scalar multiplication","level":3,"score":0.727065920829773},{"id":"https://openalex.org/C55526617","wikidata":"https://www.wikidata.org/wiki/Q719375","display_name":"Operand","level":2,"score":0.7147303223609924},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7141189575195312},{"id":"https://openalex.org/C2780595030","wikidata":"https://www.wikidata.org/wiki/Q3860309","display_name":"Multiplication (music)","level":2,"score":0.6487643122673035},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.6196213960647583},{"id":"https://openalex.org/C84211073","wikidata":"https://www.wikidata.org/wiki/Q117879","display_name":"Floating point","level":2,"score":0.5449070930480957},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.5141737461090088},{"id":"https://openalex.org/C133095886","wikidata":"https://www.wikidata.org/wiki/Q1307173","display_name":"Single-precision floating-point format","level":3,"score":0.47152289748191833},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4283389449119568},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3870163857936859},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.36903679370880127},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3514425754547119},{"id":"https://openalex.org/C57691317","wikidata":"https://www.wikidata.org/wiki/Q1289248","display_name":"Scalar (mathematics)","level":2,"score":0.33281463384628296},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3232544958591461},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3214123845100403},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.13001799583435059},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mwscas.2017.8053006","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2017.8053006","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.4300000071525574}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1580901020","https://openalex.org/W2099421191","https://openalex.org/W2117053197","https://openalex.org/W2130757597","https://openalex.org/W2331226313","https://openalex.org/W6679201360"],"related_works":["https://openalex.org/W2807524344","https://openalex.org/W2967034884","https://openalex.org/W1564887326","https://openalex.org/W4232549588","https://openalex.org/W2116803521","https://openalex.org/W3215589575","https://openalex.org/W2020888328","https://openalex.org/W2544512391","https://openalex.org/W2037018251","https://openalex.org/W2058062208"],"abstract_inverted_index":{"Scalar":[0],"addition":[1],"and":[2,7,17,65,89,99],"multiplication":[3,39,62],"generally":[4],"obey":[5],"commutative":[6],"distributive":[8],"laws.":[9],"However,":[10],"in":[11,37],"their":[12],"hardware":[13,90],"implementation,":[14],"error":[15,58],"propagation":[16],"accumulation":[18],"do":[19],"not":[20],"necessarily":[21],"follow":[22],"the":[23,35,61,94],"same":[24],"rules.":[25],"In":[26],"this":[27],"paper":[28],"we":[29],"present":[30],"a":[31,52,66,75],"statistical":[32,67],"analysis":[33,59,68],"of":[34,60,69,93,101],"accuracy":[36],"complex":[38],"approaches":[40,48],"for":[41,84],"IEEE":[42],"754":[43],"single":[44],"precision":[45],"operands.":[46],"Several":[47],"were":[49,82],"evaluated":[50],"using":[51],"dual":[53],"approach":[54],"that":[55],"included":[56],"an":[57],"operator":[63,71],"architectures":[64],"VHDL":[70],"designs,":[72,96],"implemented":[73],"on":[74],"Xilinx":[76],"Virtex":[77],"7":[78],"FPGA.":[79],"Multiple":[80],"experiments":[81],"carried":[83],"systematically":[85],"assessing":[86],"architectural,":[87],"synthesis,":[88],"performance":[91],"characteristics":[92],"target":[95],"comparing":[97],"weaknesses":[98],"strengths":[100],"each":[102],"architecture.":[103]},"counts_by_year":[{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
