{"id":"https://openalex.org/W2757981323","doi":"https://doi.org/10.1109/mwscas.2017.8052972","title":"Simulation of switching circuits using transfer functions","display_name":"Simulation of switching circuits using transfer functions","publication_year":2017,"publication_date":"2017-08-01","ids":{"openalex":"https://openalex.org/W2757981323","doi":"https://doi.org/10.1109/mwscas.2017.8052972","mag":"2757981323"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas.2017.8052972","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2017.8052972","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5079798993","display_name":"David Kebo Houngninou","orcid":"https://orcid.org/0000-0002-7017-8440"},"institutions":[{"id":"https://openalex.org/I178169726","display_name":"Southern Methodist University","ror":"https://ror.org/042tdr378","country_code":"US","type":"education","lineage":["https://openalex.org/I178169726"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"David Kebo Houngninou","raw_affiliation_strings":["Department of Computer Science and Engineering, SMU, Dallas, Texas, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, SMU, Dallas, Texas, USA","institution_ids":["https://openalex.org/I178169726"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5082009815","display_name":"Mitchell A. Thornton","orcid":"https://orcid.org/0000-0003-3559-9511"},"institutions":[{"id":"https://openalex.org/I178169726","display_name":"Southern Methodist University","ror":"https://ror.org/042tdr378","country_code":"US","type":"education","lineage":["https://openalex.org/I178169726"]},{"id":"https://openalex.org/I162577319","display_name":"The University of Texas at Dallas","ror":"https://ror.org/049emcs32","country_code":"US","type":"education","lineage":["https://openalex.org/I162577319"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mitchell A Thornton","raw_affiliation_strings":["Darwin Deason Institute for Cyber Security, SMU, Dallas, Texas, USA"],"affiliations":[{"raw_affiliation_string":"Darwin Deason Institute for Cyber Security, SMU, Dallas, Texas, USA","institution_ids":["https://openalex.org/I178169726","https://openalex.org/I162577319"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5079798993"],"corresponding_institution_ids":["https://openalex.org/I178169726"],"apc_list":null,"apc_paid":null,"fwci":0.4542,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.66242874,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"511","last_page":"514"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11450","display_name":"Model-Driven Software Engineering Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7122755646705627},{"id":"https://openalex.org/keywords/binary-decision-diagram","display_name":"Binary decision diagram","score":0.5987077355384827},{"id":"https://openalex.org/keywords/basis","display_name":"Basis (linear algebra)","score":0.531489372253418},{"id":"https://openalex.org/keywords/logic-simulation","display_name":"Logic simulation","score":0.5087063908576965},{"id":"https://openalex.org/keywords/boolean-algebra","display_name":"Boolean algebra","score":0.4766148626804352},{"id":"https://openalex.org/keywords/boolean-function","display_name":"Boolean function","score":0.46777477860450745},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.45975637435913086},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.4426746070384979},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.4410073459148407},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.43414849042892456},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.4311516582965851},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.42180579900741577},{"id":"https://openalex.org/keywords/modelica","display_name":"Modelica","score":0.411818265914917},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3752692639827728},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.2609443664550781},{"id":"https://openalex.org/keywords/simulation","display_name":"Simulation","score":0.15380927920341492},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.15000000596046448},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.14054381847381592},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.11483213305473328},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10235750675201416}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7122755646705627},{"id":"https://openalex.org/C3309909","wikidata":"https://www.wikidata.org/wiki/Q864155","display_name":"Binary decision diagram","level":2,"score":0.5987077355384827},{"id":"https://openalex.org/C12426560","wikidata":"https://www.wikidata.org/wiki/Q189569","display_name":"Basis (linear algebra)","level":2,"score":0.531489372253418},{"id":"https://openalex.org/C64859876","wikidata":"https://www.wikidata.org/wiki/Q173673","display_name":"Logic simulation","level":3,"score":0.5087063908576965},{"id":"https://openalex.org/C39685927","wikidata":"https://www.wikidata.org/wiki/Q173183","display_name":"Boolean algebra","level":2,"score":0.4766148626804352},{"id":"https://openalex.org/C187455244","wikidata":"https://www.wikidata.org/wiki/Q942353","display_name":"Boolean function","level":2,"score":0.46777477860450745},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.45975637435913086},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.4426746070384979},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.4410073459148407},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.43414849042892456},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.4311516582965851},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.42180579900741577},{"id":"https://openalex.org/C37785467","wikidata":"https://www.wikidata.org/wiki/Q385325","display_name":"Modelica","level":2,"score":0.411818265914917},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3752692639827728},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.2609443664550781},{"id":"https://openalex.org/C44154836","wikidata":"https://www.wikidata.org/wiki/Q45045","display_name":"Simulation","level":1,"score":0.15380927920341492},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.15000000596046448},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.14054381847381592},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.11483213305473328},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10235750675201416},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mwscas.2017.8052972","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2017.8052972","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1511372411","https://openalex.org/W1561934984","https://openalex.org/W2029947992","https://openalex.org/W2047650874","https://openalex.org/W2080267935","https://openalex.org/W2114536260","https://openalex.org/W2517777419","https://openalex.org/W4299910402"],"related_works":["https://openalex.org/W2357836719","https://openalex.org/W2387860042","https://openalex.org/W2352924432","https://openalex.org/W281208081","https://openalex.org/W2331379850","https://openalex.org/W4309556325","https://openalex.org/W4309834090","https://openalex.org/W2113918114","https://openalex.org/W2062085985","https://openalex.org/W2161167665"],"abstract_inverted_index":{"Simulation":[0],"of":[1,19,67,114,193,217],"complex":[2],"hardware":[3],"circuits":[4,90,105],"is":[5,13,65,136,187,206],"the":[6,20,104,112,128,139,191,200,215,218],"basis":[7,129,224],"for":[8,86,130,148,225],"many":[9],"EDA":[10,146,226],"tasks":[11],"and":[12,33,37,167,212],"commonly":[14],"used":[15,126,207],"at":[16],"various":[17],"phases":[18],"design":[21],"flow.":[22],"State-of-the-art":[23],"simulation":[24,31,40,63,132],"tools":[25,64,155],"are":[26,34,106],"based":[27,53,94],"upon":[28,95],"discrete":[29,47],"event":[30,48],"algorithms":[32],"highly":[35],"optimized":[36],"mature.":[38],"Symbolic":[39],"may":[41,75],"also":[42],"be":[43,76,124],"implemented":[44],"using":[45],"a":[46,68,131,143,164,168,223],"approach,":[49],"or":[50,70],"other":[51],"approaches":[52],"on":[54],"extracted":[55],"functional":[56],"models.":[57],"The":[58],"common":[59],"foundation":[60],"behind":[61],"modern":[62],"that":[66,74,120],"switching":[69,101],"Boolean":[71,100],"algebraic":[72,220],"model":[73,85,122,221],"augmented":[77],"with":[78],"timing":[79],"information.":[80],"Recently,":[81],"an":[82],"alternative":[83],"foundational":[84],"conventional":[87],"digital":[88],"electronic":[89],"has":[91],"been":[92],"proposed,":[93],"linear":[96,115,219],"algebra":[97,102],"rather":[98],"than":[99],"where":[103],"modeled":[107],"as":[108,127,157,182,222],"transfer":[109,183,201],"functions":[110],"in":[111],"form":[113],"transformation":[116],"matrices.":[117],"We":[118],"demonstrate":[119],"this":[121],"can":[123],"effectively":[125],"methodology.":[133],"Our":[134,171],"approach":[135],"motivated":[137],"by":[138],"need":[140],"to":[141,176,198,208,213],"develop":[142],"truly":[144],"unified":[145],"tool":[147],"mixed":[149,178],"signal":[150,179],"circuit":[151,180],"design.":[152],"Currently,":[153],"industrial":[154],"such":[156],"SPECTRE":[158],"use":[159,192],"two":[160],"different":[161],"internal":[162],"engines;":[163],"SPICE-like":[165],"engine":[166],"Verilog-like":[169],"engine.":[170],"method":[172],"will":[173],"allow":[174],"us":[175],"represent":[177,199],"elements":[181],"functions.":[184,202],"Spatial":[185],"complexity":[186],"significantly":[188],"reduced":[189],"through":[190],"binary":[194],"decision":[195],"diagrams":[196],"(BDD)":[197],"A":[203],"prototype":[204],"implementation":[205],"generate":[209],"experimental":[210],"results":[211],"illustrate":[214],"viability":[216],"applications.":[227]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}