{"id":"https://openalex.org/W2757665404","doi":"https://doi.org/10.1109/mwscas.2017.8052965","title":"Embedded FFT hardware algorithm development using automated bi-dimensional scalable folding","display_name":"Embedded FFT hardware algorithm development using automated bi-dimensional scalable folding","publication_year":2017,"publication_date":"2017-08-01","ids":{"openalex":"https://openalex.org/W2757665404","doi":"https://doi.org/10.1109/mwscas.2017.8052965","mag":"2757665404"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas.2017.8052965","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2017.8052965","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5021231544","display_name":"Felipe Minotta","orcid":"https://orcid.org/0000-0002-8746-4013"},"institutions":[{"id":"https://openalex.org/I60388903","display_name":"University of Puerto Rico-Mayaguez","ror":"https://ror.org/00wek6x04","country_code":"PR","type":"education","lineage":["https://openalex.org/I200399037","https://openalex.org/I60388903"]}],"countries":["PR"],"is_corresponding":true,"raw_author_name":"Felipe Minotta","raw_affiliation_strings":["Electrical and Computer Engineering Department, University of Puerto Rico at Mayaguez"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, University of Puerto Rico at Mayaguez","institution_ids":["https://openalex.org/I60388903"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100599698","display_name":"Manuel Jim\u00e9nez","orcid":"https://orcid.org/0000-0003-0497-1480"},"institutions":[{"id":"https://openalex.org/I60388903","display_name":"University of Puerto Rico-Mayaguez","ror":"https://ror.org/00wek6x04","country_code":"PR","type":"education","lineage":["https://openalex.org/I200399037","https://openalex.org/I60388903"]}],"countries":["PR"],"is_corresponding":false,"raw_author_name":"Manuel Jimenez","raw_affiliation_strings":["Electrical and Computer Engineering Department, University of Puerto Rico at Mayaguez"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, University of Puerto Rico at Mayaguez","institution_ids":["https://openalex.org/I60388903"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101793593","display_name":"Domingo Rodr\u0131\u0301guez","orcid":"https://orcid.org/0000-0003-0493-5156"},"institutions":[{"id":"https://openalex.org/I60388903","display_name":"University of Puerto Rico-Mayaguez","ror":"https://ror.org/00wek6x04","country_code":"PR","type":"education","lineage":["https://openalex.org/I200399037","https://openalex.org/I60388903"]}],"countries":["PR"],"is_corresponding":false,"raw_author_name":"Domingo Rodriguez","raw_affiliation_strings":["Electrical and Computer Engineering Department, University of Puerto Rico at Mayaguez"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering Department, University of Puerto Rico at Mayaguez","institution_ids":["https://openalex.org/I60388903"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5021231544"],"corresponding_institution_ids":["https://openalex.org/I60388903"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.12640585,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"483","last_page":"486"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9962000250816345,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9876999855041504,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.795451819896698},{"id":"https://openalex.org/keywords/fast-fourier-transform","display_name":"Fast Fourier transform","score":0.7428135871887207},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6821266412734985},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6141443252563477},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.502159833908081},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.45400285720825195},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4268152117729187},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3452044129371643}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.795451819896698},{"id":"https://openalex.org/C75172450","wikidata":"https://www.wikidata.org/wiki/Q623950","display_name":"Fast Fourier transform","level":2,"score":0.7428135871887207},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6821266412734985},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6141443252563477},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.502159833908081},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.45400285720825195},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4268152117729187},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3452044129371643},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mwscas.2017.8052965","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2017.8052965","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5299999713897705,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1977482330","https://openalex.org/W1979502974","https://openalex.org/W1988238773","https://openalex.org/W1989522161","https://openalex.org/W1993834099","https://openalex.org/W1996712243","https://openalex.org/W2024381286","https://openalex.org/W2045810654","https://openalex.org/W2061171222","https://openalex.org/W2082275189","https://openalex.org/W2109070029","https://openalex.org/W2494882022","https://openalex.org/W2511276075","https://openalex.org/W2512116931"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W4327521644","https://openalex.org/W2978884468","https://openalex.org/W3132558499","https://openalex.org/W2005846134","https://openalex.org/W2355315220","https://openalex.org/W4200391368","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506"],"abstract_inverted_index":{"This":[0,42],"paper":[1,58,73],"presents":[2,59,75],"an":[3],"original":[4],"and":[5,17,31,67,77,90],"unique":[6],"embedded":[7],"FFT":[8,39,55],"hardware":[9,40,91],"algorithm":[10,30],"development":[11],"process":[12],"based":[13],"on":[14,98],"a":[15,36,46],"systematic":[16],"scalable":[18],"procedure":[19,47],"for":[20,25,93],"generating":[21],"permutation-based":[22],"address":[23,64],"patterns":[24],"any":[26,32],"power-of-2":[27],"transform":[28],"size":[29],"folding":[33],"factor":[34],"in":[35,84],"Kronecker":[37,54],"Pease":[38],"implementation.":[41],"is":[43],"coupled":[44],"by":[45],"to":[48],"perform":[49],"automatic":[50],"code":[51],"generation":[52,66],"of":[53,79,86],"cores.":[56],"The":[57,72],"important":[60],"results":[61],"about":[62],"twiddle":[63],"pattern":[65],"data":[68],"switch":[69],"multiplexing":[70],"techniques.":[71],"also":[74],"analyses":[76],"comparisons":[78],"the":[80,99],"architecture":[81],"design":[82],"performance":[83],"terms":[85],"clock":[87],"latency,":[88],"accuracy,":[89],"resources":[92],"benchmarking":[94],"implementation":[95],"efforts":[96],"performed":[97],"Xilinx":[100],"Virtex-7":[101],"FPGA.":[102]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}