{"id":"https://openalex.org/W2593589223","doi":"https://doi.org/10.1109/mwscas.2016.7870152","title":"Routability of twisted common-centroid capacitor array under signal coupling constraints","display_name":"Routability of twisted common-centroid capacitor array under signal coupling constraints","publication_year":2016,"publication_date":"2016-10-01","ids":{"openalex":"https://openalex.org/W2593589223","doi":"https://doi.org/10.1109/mwscas.2016.7870152","mag":"2593589223"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas.2016.7870152","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2016.7870152","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100389842","display_name":"Gong Chen","orcid":"https://orcid.org/0000-0003-1440-990X"},"institutions":[{"id":"https://openalex.org/I24201400","display_name":"Chengdu University of Information Technology","ror":"https://ror.org/01yxwrh59","country_code":"CN","type":"education","lineage":["https://openalex.org/I24201400"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Gong Chen","raw_affiliation_strings":["Chengdu University of Information Technology"],"affiliations":[{"raw_affiliation_string":"Chengdu University of Information Technology","institution_ids":["https://openalex.org/I24201400"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100461643","display_name":"Bo Liu","orcid":"https://orcid.org/0000-0002-3093-4571"},"institutions":[{"id":"https://openalex.org/I17056963","display_name":"The University of Kitakyushu","ror":"https://ror.org/03mfefw72","country_code":"JP","type":"education","lineage":["https://openalex.org/I17056963"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Bo Liu","raw_affiliation_strings":["The University of Kitakyushu"],"affiliations":[{"raw_affiliation_string":"The University of Kitakyushu","institution_ids":["https://openalex.org/I17056963"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000531897","display_name":"Shigetoshi Nakatake","orcid":null},"institutions":[{"id":"https://openalex.org/I17056963","display_name":"The University of Kitakyushu","ror":"https://ror.org/03mfefw72","country_code":"JP","type":"education","lineage":["https://openalex.org/I17056963"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Shigetoshi Nakatake","raw_affiliation_strings":["The University of Kitakyushu"],"affiliations":[{"raw_affiliation_string":"The University of Kitakyushu","institution_ids":["https://openalex.org/I17056963"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5065368480","display_name":"Bo Yang","orcid":"https://orcid.org/0000-0001-7961-853X"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Bo Yang","raw_affiliation_strings":["Design Algorithm Laboratory, Inc"],"affiliations":[{"raw_affiliation_string":"Design Algorithm Laboratory, Inc","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5100389842"],"corresponding_institution_ids":["https://openalex.org/I24201400"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.17482223,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.851077675819397},{"id":"https://openalex.org/keywords/capacitance","display_name":"Capacitance","score":0.7149814367294312},{"id":"https://openalex.org/keywords/centroid","display_name":"Centroid","score":0.6647082567214966},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5275915265083313},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.45737409591674805},{"id":"https://openalex.org/keywords/coupling","display_name":"Coupling (piping)","score":0.43245330452919006},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.36342334747314453},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.31721925735473633},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.20072883367538452},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.15439355373382568},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.12438678741455078},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.09927189350128174}],"concepts":[{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.851077675819397},{"id":"https://openalex.org/C30066665","wikidata":"https://www.wikidata.org/wiki/Q164399","display_name":"Capacitance","level":3,"score":0.7149814367294312},{"id":"https://openalex.org/C146599234","wikidata":"https://www.wikidata.org/wiki/Q511093","display_name":"Centroid","level":2,"score":0.6647082567214966},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5275915265083313},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.45737409591674805},{"id":"https://openalex.org/C131584629","wikidata":"https://www.wikidata.org/wiki/Q4308705","display_name":"Coupling (piping)","level":2,"score":0.43245330452919006},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.36342334747314453},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.31721925735473633},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.20072883367538452},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.15439355373382568},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.12438678741455078},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.09927189350128174},{"id":"https://openalex.org/C17525397","wikidata":"https://www.wikidata.org/wiki/Q176140","display_name":"Electrode","level":2,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mwscas.2016.7870152","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2016.7870152","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.6399999856948853}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1594101521","https://openalex.org/W1998284495","https://openalex.org/W2019437651","https://openalex.org/W2040154714","https://openalex.org/W2103937095","https://openalex.org/W2162637605","https://openalex.org/W2163310585","https://openalex.org/W4237435002","https://openalex.org/W6655040866","https://openalex.org/W6683934493"],"related_works":["https://openalex.org/W2381926679","https://openalex.org/W2007009951","https://openalex.org/W2082644203","https://openalex.org/W2350539780","https://openalex.org/W2080773395","https://openalex.org/W3212531278","https://openalex.org/W2099626417","https://openalex.org/W2019514496","https://openalex.org/W2085450379","https://openalex.org/W2354552488"],"abstract_inverted_index":{"We":[0,35],"address":[1],"layout":[2,41],"generation":[3,55],"of":[4,17,43],"on-chip":[5],"matched":[6],"capacitors":[7,19],"with":[8,48],"the":[9,21,40,49],"high":[10],"relative":[11],"accuracy.":[12],"Our":[13],"twisted":[14],"common-centroid":[15],"pattern":[16],"unit":[18],"consider":[20],"post-placement":[22],"routability":[23,70],"as":[24,26],"well":[25],"reduce":[27],"a":[28,59,68],"systematic":[29],"mismatch":[30],"induced":[31],"by":[32],"process":[33],"gradient.":[34],"apply":[36],"this":[37],"algorithm":[38],"to":[39],"design":[42],"an":[44],"SAR-ADC":[45],"circuit.":[46],"Compared":[47],"common":[50],"spiral":[51],"capacitor":[52],"array,":[53],"our":[54],"method":[56],"(1)":[57],"produces":[58],"similar":[60],"low":[61],"capacitance":[62],"ration":[63],"mismatch,":[64],"and":[65],"moreover":[66],"(2)":[67],"100%":[69],"can":[71],"be":[72],"achieved.":[73]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
