{"id":"https://openalex.org/W2591685570","doi":"https://doi.org/10.1109/mwscas.2016.7870147","title":"Synthesis and evaluation of SHA-1 algorithm using altera SDK for OpenCL","display_name":"Synthesis and evaluation of SHA-1 algorithm using altera SDK for OpenCL","publication_year":2016,"publication_date":"2016-10-01","ids":{"openalex":"https://openalex.org/W2591685570","doi":"https://doi.org/10.1109/mwscas.2016.7870147","mag":"2591685570"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas.2016.7870147","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2016.7870147","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5046506096","display_name":"Ian Janik","orcid":null},"institutions":[{"id":"https://openalex.org/I74413500","display_name":"University of Windsor","ror":"https://ror.org/01gw3d370","country_code":"CA","type":"education","lineage":["https://openalex.org/I74413500"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Ian Janik","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Windsor, Windsor, Ontario, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Windsor, Windsor, Ontario, Canada","institution_ids":["https://openalex.org/I74413500"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5074437075","display_name":"Mohammed Khalid","orcid":"https://orcid.org/0000-0003-3903-8789"},"institutions":[{"id":"https://openalex.org/I74413500","display_name":"University of Windsor","ror":"https://ror.org/01gw3d370","country_code":"CA","type":"education","lineage":["https://openalex.org/I74413500"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Mohammed A. S. Khalid","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Windsor, Windsor, Ontario, Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Windsor, Windsor, Ontario, Canada","institution_ids":["https://openalex.org/I74413500"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5046506096"],"corresponding_institution_ids":["https://openalex.org/I74413500"],"apc_list":null,"apc_paid":null,"fwci":0.4285,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.80913053,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11130","display_name":"Coding theory and cryptography","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11797","display_name":"graph theory and CDMA systems","score":0.9866999983787537,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8505914211273193},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.8480421304702759},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7771766781806946},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.6749897003173828},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5851736068725586},{"id":"https://openalex.org/keywords/hash-function","display_name":"Hash function","score":0.5326254963874817},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.518509030342102},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.46146538853645325},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4579772353172302},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.38989517092704773},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1584130823612213}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8505914211273193},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.8480421304702759},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7771766781806946},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.6749897003173828},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5851736068725586},{"id":"https://openalex.org/C99138194","wikidata":"https://www.wikidata.org/wiki/Q183427","display_name":"Hash function","level":2,"score":0.5326254963874817},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.518509030342102},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.46146538853645325},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4579772353172302},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.38989517092704773},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1584130823612213},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mwscas.2016.7870147","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2016.7870147","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4300000071525574,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1559467217","https://openalex.org/W1939171670","https://openalex.org/W1998157369","https://openalex.org/W2010639041","https://openalex.org/W2100121196","https://openalex.org/W2399715892","https://openalex.org/W2540913466","https://openalex.org/W2619725017"],"related_works":["https://openalex.org/W4281926497","https://openalex.org/W2612099726","https://openalex.org/W2269990635","https://openalex.org/W2108242004","https://openalex.org/W4312985392","https://openalex.org/W2042762783","https://openalex.org/W4283730710","https://openalex.org/W4281784598","https://openalex.org/W4313484792","https://openalex.org/W2921149022"],"abstract_inverted_index":{"This":[0,115],"paper":[1,52,72],"uses":[2],"the":[3,15,18,57,67,78,82,101,120,143],"Altera":[4],"SDK":[5],"for":[6],"OpenCL":[7],"(AOCL)":[8],"High-Level":[9],"Synthesis":[10],"(HLS)":[11],"tool":[12],"to":[13,24,54,66,94,99,107,119],"accelerate":[14],"computation":[16],"of":[17,27,50,64,81,112,134],"SHA-1":[19,83],"hash":[20],"function.":[21],"Using":[22],"FPGAs":[23],"increase":[25],"throughput":[26,111,133],"this":[28,51],"algorithm":[29,84],"has":[30,130],"been":[31],"a":[32,109,131,138],"popular":[33],"topic":[34],"in":[35,62,124],"research.":[36],"The":[37,48,71,87,103,127],"work":[38],"done":[39],"thus":[40],"far,":[41],"focuses":[42],"on":[43],"HDL":[44,68,121],"based":[45,69,122],"design":[46,79],"methodologies.":[47],"goal":[49],"is":[53,91,117],"determine":[55],"if":[56],"HLS":[58,104],"implementation":[59,105,129],"can":[60],"compare":[61],"terms":[63],"speed":[65,116],"designs.":[70],"presents":[73],"results":[74],"obtained":[75],"by":[76],"exploring":[77],"space":[80],"using":[85],"AOCL.":[86],"FPGA":[88,144],"accelerated":[89,145],"program":[90],"also":[92],"compared":[93],"an":[95],"equivalent":[96],"CPU":[97,128],"version":[98],"measure":[100],"speedup.":[102],"managed":[106],"achieve":[108],"maximum":[110,132],"3033":[113],"Mbps.":[114],"comparable":[118],"designs":[123],"published":[125],"literature.":[126],"217":[135],"Mbps,":[136],"giving":[137],"14":[139],"times":[140],"speedup":[141],"with":[142],"program.":[146]},"counts_by_year":[{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}