{"id":"https://openalex.org/W2593248802","doi":"https://doi.org/10.1109/mwscas.2016.7870097","title":"Toward better layout design in ASTRAN CAD tool by using an efficient transistor folding","display_name":"Toward better layout design in ASTRAN CAD tool by using an efficient transistor folding","publication_year":2016,"publication_date":"2016-10-01","ids":{"openalex":"https://openalex.org/W2593248802","doi":"https://doi.org/10.1109/mwscas.2016.7870097","mag":"2593248802"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas.2016.7870097","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2016.7870097","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5041919625","display_name":"Gustavo H. Smaniotto","orcid":"https://orcid.org/0000-0002-0862-3910"},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":true,"raw_author_name":"Gustavo H. Smaniotto","raw_affiliation_strings":["Universidade Federal de Pelotas, Pelotas, Brazil"],"affiliations":[{"raw_affiliation_string":"Universidade Federal de Pelotas, Pelotas, Brazil","institution_ids":["https://openalex.org/I169248161"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101963901","display_name":"Matheus T. Moreira","orcid":"https://orcid.org/0000-0001-5030-9215"},"institutions":[{"id":"https://openalex.org/I45643870","display_name":"Pontif\u00edcia Universidade Cat\u00f3lica do Rio Grande do Sul","ror":"https://ror.org/025vmq686","country_code":"BR","type":"education","lineage":["https://openalex.org/I45643870"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Matheus T. Moreira","raw_affiliation_strings":["Pontificia Universidade Cat\u00f3lica do Rio Grande do Sul, Porto, Alegre, Brazil"],"affiliations":[{"raw_affiliation_string":"Pontificia Universidade Cat\u00f3lica do Rio Grande do Sul, Porto, Alegre, Brazil","institution_ids":["https://openalex.org/I45643870"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023900574","display_name":"Adriel Ziesemer","orcid":null},"institutions":[{"id":"https://openalex.org/I2801049591","display_name":"Instituto Federal de Educa\u00e7\u00e3o, Ci\u00eancia e Tecnologia do Rio Grande do Sul","ror":"https://ror.org/008p1v134","country_code":"BR","type":"education","lineage":["https://openalex.org/I1293487690","https://openalex.org/I2801049591","https://openalex.org/I2801200668"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Adriel M. Ziesemer","raw_affiliation_strings":["Institnto Federal do Rio Grande do Sul, Canoas, Brazil"],"affiliations":[{"raw_affiliation_string":"Institnto Federal do Rio Grande do Sul, Canoas, Brazil","institution_ids":["https://openalex.org/I2801049591"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068796829","display_name":"Felipe Marques","orcid":"https://orcid.org/0000-0003-1318-9992"},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Felipe S. Marques","raw_affiliation_strings":["Universidade Federal de Pelotas, Pelotas, Brazil"],"affiliations":[{"raw_affiliation_string":"Universidade Federal de Pelotas, Pelotas, Brazil","institution_ids":["https://openalex.org/I169248161"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5014303947","display_name":"Leomar S. da Rosa","orcid":"https://orcid.org/0000-0002-7150-5685"},"institutions":[{"id":"https://openalex.org/I169248161","display_name":"Universidade Federal de Pelotas","ror":"https://ror.org/05msy9z54","country_code":"BR","type":"education","lineage":["https://openalex.org/I169248161"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Leomar S. da Rosa","raw_affiliation_strings":["Universidade Federal de Pelotas, Pelotas, Brazil"],"affiliations":[{"raw_affiliation_string":"Universidade Federal de Pelotas, Pelotas, Brazil","institution_ids":["https://openalex.org/I169248161"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5041919625"],"corresponding_institution_ids":["https://openalex.org/I169248161"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.17442651,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/folding","display_name":"Folding (DSP implementation)","score":0.7498648762702942},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.7466572523117065},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.7432951927185059},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6796115636825562},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.648165225982666},{"id":"https://openalex.org/keywords/limit","display_name":"Limit (mathematics)","score":0.5451177954673767},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.5075887441635132},{"id":"https://openalex.org/keywords/page-layout","display_name":"Page layout","score":0.4616142511367798},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.45350196957588196},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.44358277320861816},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.44141268730163574},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.4363342225551605},{"id":"https://openalex.org/keywords/cad","display_name":"CAD","score":0.42930108308792114},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.4087934195995331},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.39371347427368164},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.2728453278541565},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2167406678199768},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.21106389164924622},{"id":"https://openalex.org/keywords/engineering-drawing","display_name":"Engineering drawing","score":0.2018757462501526},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.19317489862442017},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15378642082214355},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.11906927824020386}],"concepts":[{"id":"https://openalex.org/C2776545253","wikidata":"https://www.wikidata.org/wiki/Q5464292","display_name":"Folding (DSP implementation)","level":2,"score":0.7498648762702942},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.7466572523117065},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.7432951927185059},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6796115636825562},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.648165225982666},{"id":"https://openalex.org/C151201525","wikidata":"https://www.wikidata.org/wiki/Q177239","display_name":"Limit (mathematics)","level":2,"score":0.5451177954673767},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.5075887441635132},{"id":"https://openalex.org/C188985296","wikidata":"https://www.wikidata.org/wiki/Q868954","display_name":"Page layout","level":2,"score":0.4616142511367798},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.45350196957588196},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.44358277320861816},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.44141268730163574},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.4363342225551605},{"id":"https://openalex.org/C194789388","wikidata":"https://www.wikidata.org/wiki/Q17855283","display_name":"CAD","level":2,"score":0.42930108308792114},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.4087934195995331},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.39371347427368164},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2728453278541565},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2167406678199768},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.21106389164924622},{"id":"https://openalex.org/C199639397","wikidata":"https://www.wikidata.org/wiki/Q1788588","display_name":"Engineering drawing","level":1,"score":0.2018757462501526},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.19317489862442017},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15378642082214355},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.11906927824020386},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C144133560","wikidata":"https://www.wikidata.org/wiki/Q4830453","display_name":"Business","level":0,"score":0.0},{"id":"https://openalex.org/C112698675","wikidata":"https://www.wikidata.org/wiki/Q37038","display_name":"Advertising","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mwscas.2016.7870097","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2016.7870097","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1972270843","https://openalex.org/W2018989845","https://openalex.org/W2022575517","https://openalex.org/W2031753133","https://openalex.org/W2041242877","https://openalex.org/W2043780523","https://openalex.org/W2078179095","https://openalex.org/W2093491063","https://openalex.org/W2126311241","https://openalex.org/W2166639234"],"related_works":["https://openalex.org/W2091329789","https://openalex.org/W2376726667","https://openalex.org/W2357425846","https://openalex.org/W162881505","https://openalex.org/W1873584906","https://openalex.org/W2466238913","https://openalex.org/W583900352","https://openalex.org/W1464706131","https://openalex.org/W2376028644","https://openalex.org/W2125213949"],"abstract_inverted_index":{"Traditional":[0],"synthesis":[1,45],"flows":[2],"dedicated":[3],"to":[4,13,25,64,116],"design":[5],"ASICs":[6],"usually":[7],"adopt":[8],"the":[9,26,33,71,75,86,91,94,117,147],"standard":[10],"cell":[11,55],"approach":[12,115,138],"generate":[14],"VLSI":[15],"circuits.":[16],"Consequently,":[17],"chip-level":[18],"layout":[19,92],"is":[20,74,99],"not":[21],"fully":[22],"optimized":[23],"due":[24],"restricted":[27],"number":[28],"of":[29,93,130],"cells":[30],"present":[31],"in":[32,80,101,141,146],"library.":[34],"To":[35],"reduce":[36],"this":[37,97,110,137],"problem,":[38],"ASTRAN,":[39],"an":[40],"academic":[41],"open":[42],"source":[43],"automatic":[44],"tool,":[46],"was":[47],"developed.":[48],"This":[49,107],"tool":[50],"generates":[51],"layouts":[52],"with":[53,60],"generic":[54],"structures":[56],"and":[57,125,143],"obtains":[58],"results":[59,134],"similar":[61],"density":[62],"compared":[63],"handcrafted":[65],"cells.":[66,95],"A":[67],"key":[68],"step":[69,98],"on":[70],"ASTRAN":[72,102],"flow":[73],"transistor":[76],"folding,":[77],"which":[78,120],"consists":[79],"breaking":[81],"larger":[82],"transistors":[83,123],"that":[84],"exceed":[85],"maximum":[87],"height":[88],"limit":[89],"for":[90,128],"However,":[96],"executed":[100],"only":[103],"into":[104],"single":[105],"transistors.":[106],"work":[108],"optimizes":[109],"strategy":[111],"introducing":[112],"a":[113],"new":[114],"folding":[118,127],"technique,":[119],"identifies":[121],"all":[122],"stacks":[124],"applies":[126],"each":[129],"these":[131],"arrangements.":[132],"The":[133],"obtained":[135],"through":[136],"show":[139],"reductions":[140],"geometrical":[142],"electrical":[144],"aspects":[145],"layout.":[148]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
