{"id":"https://openalex.org/W2593504957","doi":"https://doi.org/10.1109/mwscas.2016.7869994","title":"A low cost, constant throughput and reusable 8#x00D7;8 DCT architecture for HEVC","display_name":"A low cost, constant throughput and reusable 8#x00D7;8 DCT architecture for HEVC","publication_year":2016,"publication_date":"2016-10-01","ids":{"openalex":"https://openalex.org/W2593504957","doi":"https://doi.org/10.1109/mwscas.2016.7869994","mag":"2593504957"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas.2016.7869994","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2016.7869994","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103240381","display_name":"Subiman Chatterjee","orcid":"https://orcid.org/0000-0001-8957-741X"},"institutions":[{"id":"https://openalex.org/I91357014","display_name":"Banaras Hindu University","ror":"https://ror.org/04cdn2797","country_code":"IN","type":"education","lineage":["https://openalex.org/I91357014"]},{"id":"https://openalex.org/I56404289","display_name":"Indian Institute of Technology BHU","ror":"https://ror.org/01kh5gc44","country_code":"IN","type":"education","lineage":["https://openalex.org/I56404289"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Subiman Chatterjee","raw_affiliation_strings":["Dept. of Electronics Engineering, Indian Institute of Technology (BHU), Varanasi, India"],"affiliations":[{"raw_affiliation_string":"Dept. of Electronics Engineering, Indian Institute of Technology (BHU), Varanasi, India","institution_ids":["https://openalex.org/I56404289","https://openalex.org/I91357014"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5054081739","display_name":"Kishor Sarawadekar","orcid":"https://orcid.org/0000-0001-8230-6481"},"institutions":[{"id":"https://openalex.org/I56404289","display_name":"Indian Institute of Technology BHU","ror":"https://ror.org/01kh5gc44","country_code":"IN","type":"education","lineage":["https://openalex.org/I56404289"]},{"id":"https://openalex.org/I91357014","display_name":"Banaras Hindu University","ror":"https://ror.org/04cdn2797","country_code":"IN","type":"education","lineage":["https://openalex.org/I91357014"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Kishor Prabhakar Sarawadekar","raw_affiliation_strings":["Dept. of Electronics Engineering, Indian Institute of Technology (BHU), Varanasi, India"],"affiliations":[{"raw_affiliation_string":"Dept. of Electronics Engineering, Indian Institute of Technology (BHU), Varanasi, India","institution_ids":["https://openalex.org/I56404289","https://openalex.org/I91357014"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5103240381"],"corresponding_institution_ids":["https://openalex.org/I56404289","https://openalex.org/I91357014"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.19965464,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10741","display_name":"Video Coding and Compression Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10741","display_name":"Video Coding and Compression Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10901","display_name":"Advanced Data Compression Techniques","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/discrete-cosine-transform","display_name":"Discrete cosine transform","score":0.9054657220840454},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7363913059234619},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6265652179718018},{"id":"https://openalex.org/keywords/coding","display_name":"Coding (social sciences)","score":0.6251659393310547},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5323009490966797},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.5033521056175232},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.45406243205070496},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.4519221782684326},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.43334531784057617},{"id":"https://openalex.org/keywords/hardware-architecture","display_name":"Hardware architecture","score":0.42854565382003784},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3482569456100464},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.15683606266975403},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.13749444484710693},{"id":"https://openalex.org/keywords/image","display_name":"Image (mathematics)","score":0.09866371750831604},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.07154697179794312}],"concepts":[{"id":"https://openalex.org/C2221639","wikidata":"https://www.wikidata.org/wiki/Q2877","display_name":"Discrete cosine transform","level":3,"score":0.9054657220840454},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7363913059234619},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6265652179718018},{"id":"https://openalex.org/C179518139","wikidata":"https://www.wikidata.org/wiki/Q5140297","display_name":"Coding (social sciences)","level":2,"score":0.6251659393310547},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5323009490966797},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.5033521056175232},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.45406243205070496},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.4519221782684326},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.43334531784057617},{"id":"https://openalex.org/C65232700","wikidata":"https://www.wikidata.org/wiki/Q5656403","display_name":"Hardware architecture","level":3,"score":0.42854565382003784},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3482569456100464},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.15683606266975403},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.13749444484710693},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.09866371750831604},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.07154697179794312},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mwscas.2016.7869994","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2016.7869994","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8600000143051147}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1980792802","https://openalex.org/W1981542807","https://openalex.org/W1994676015","https://openalex.org/W2005330886","https://openalex.org/W2082301295","https://openalex.org/W2084086197","https://openalex.org/W2105815873","https://openalex.org/W2146395539","https://openalex.org/W2154465656","https://openalex.org/W2177444257"],"related_works":["https://openalex.org/W1916685473","https://openalex.org/W2055682261","https://openalex.org/W1993363272","https://openalex.org/W2186390138","https://openalex.org/W2060035984","https://openalex.org/W2790129917","https://openalex.org/W2992856432","https://openalex.org/W2100638064","https://openalex.org/W2281932057","https://openalex.org/W1811003797"],"abstract_inverted_index":{"High":[0],"Efficiency":[1],"Video":[2],"Coding":[3],"(HEVC)":[4],"standard":[5],"uses":[6],"Discrete":[7],"Cosine":[8],"Transform":[9,19],"(DCT)":[10],"to":[11,73,85],"compress":[12],"energy.":[13],"The":[14,113,121],"minimum":[15],"and":[16,30,57,106],"the":[17,46,98,140],"maximum":[18],"Unit":[20],"(TU)":[21],"size":[22,38],"used":[23],"in":[24],"HEVC":[25],"is":[26,44,60,83,104,109,116],"4":[27,29,75,89],"\u00d7":[28,32,152],"32":[31],"32,":[33],"respectively.":[34],"With":[35],"large":[36],"TU":[37],"coding":[39],"efficiency":[40],"improves.":[41],"But,":[42],"it":[43,82],"at":[45,126,134],"cost":[47],"of":[48,149],"increased":[49,110],"hardware":[50,55],"complexity.":[51],"Further,":[52],"achieving":[53],"full":[54],"utilization":[56,108],"constant":[58,102],"throughput":[59,103],"a":[61,80],"challenging":[62],"task.":[63],"In":[64],"this":[65],"paper,":[66],"8":[67,93],"point":[68,76,90,94],"DCT":[69,77,95,123,131,143],"expressions":[70],"are":[71],"tweaked":[72],"obtain":[74],"equations.":[78],"As":[79],"consequence,":[81],"possible":[84],"compute":[86],"either":[87],"two":[88],"or":[91],"one":[92],"operation":[96],"using":[97],"same":[99],"architecture.":[100],"Additionally,":[101],"achieved":[105],"memory":[107],"by":[111],"25%.":[112],"proposed":[114,141],"architecture":[115,124,132,144],"implemented":[117],"on":[118],"FPGA":[119],"platform.":[120],"1D":[122],"operates":[125],"183.3":[127],"MHz,":[128],"whereas":[129],"2D":[130,142],"works":[133],"145.1":[135],"MHz.":[136],"This":[137],"entails":[138],"that":[139],"can":[145],"process":[146],"46":[147],"fps":[148],"UHD":[150],"(3840":[151],"2160)":[153],"video.":[154]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}