{"id":"https://openalex.org/W1651218569","doi":"https://doi.org/10.1109/mwscas.2015.7282061","title":"A 12-bit 20-MS/s SAR ADC with improved internal clock generator and SAR controller","display_name":"A 12-bit 20-MS/s SAR ADC with improved internal clock generator and SAR controller","publication_year":2015,"publication_date":"2015-08-01","ids":{"openalex":"https://openalex.org/W1651218569","doi":"https://doi.org/10.1109/mwscas.2015.7282061","mag":"1651218569"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas.2015.7282061","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2015.7282061","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100362376","display_name":"Xuan Li","orcid":"https://orcid.org/0000-0003-4079-1380"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Xuan Li","raw_affiliation_strings":["Information and Electrical Engineering, Shanghai Jiao Tong University, Shanghai, China","[School of Electronic Information and Electrical Engineering, Shanghai Jiao Tong University, China]"],"affiliations":[{"raw_affiliation_string":"Information and Electrical Engineering, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]},{"raw_affiliation_string":"[School of Electronic Information and Electrical Engineering, Shanghai Jiao Tong University, China]","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019099711","display_name":"Shuo Huang","orcid":"https://orcid.org/0000-0002-3730-8485"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shuo Huang","raw_affiliation_strings":["Information and Electrical Engineering, Shanghai Jiao Tong University, Shanghai, China","[School of Electronic Information and Electrical Engineering, Shanghai Jiao Tong University, China]"],"affiliations":[{"raw_affiliation_string":"Information and Electrical Engineering, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]},{"raw_affiliation_string":"[School of Electronic Information and Electrical Engineering, Shanghai Jiao Tong University, China]","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091076746","display_name":"Jianjun Zhou","orcid":"https://orcid.org/0000-0001-9898-7285"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Jianjun Zhou","raw_affiliation_strings":["Information and Electrical Engineering, Shanghai Jiao Tong University, Shanghai, China","[School of Electronic Information and Electrical Engineering, Shanghai Jiao Tong University, China]"],"affiliations":[{"raw_affiliation_string":"Information and Electrical Engineering, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]},{"raw_affiliation_string":"[School of Electronic Information and Electrical Engineering, Shanghai Jiao Tong University, China]","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100673957","display_name":"Xiaoyong Li","orcid":"https://orcid.org/0000-0003-2664-8553"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaoyong Li","raw_affiliation_strings":["Information and Electrical Engineering, Shanghai Jiao Tong University, Shanghai, China","[School of Electronic Information and Electrical Engineering, Shanghai Jiao Tong University, China]"],"affiliations":[{"raw_affiliation_string":"Information and Electrical Engineering, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]},{"raw_affiliation_string":"[School of Electronic Information and Electrical Engineering, Shanghai Jiao Tong University, China]","institution_ids":["https://openalex.org/I183067930"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5100362376"],"corresponding_institution_ids":["https://openalex.org/I183067930"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.0311795,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"30","issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/spurious-free-dynamic-range","display_name":"Spurious-free dynamic range","score":0.9089717864990234},{"id":"https://openalex.org/keywords/successive-approximation-adc","display_name":"Successive approximation ADC","score":0.8761112689971924},{"id":"https://openalex.org/keywords/clock-generator","display_name":"Clock generator","score":0.7314088344573975},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6463616490364075},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5606332421302795},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5590436458587646},{"id":"https://openalex.org/keywords/analog-to-digital-converter","display_name":"Analog-to-digital converter","score":0.4664169251918793},{"id":"https://openalex.org/keywords/settling-time","display_name":"Settling time","score":0.4604305624961853},{"id":"https://openalex.org/keywords/12-bit","display_name":"12-bit","score":0.4589551091194153},{"id":"https://openalex.org/keywords/controller","display_name":"Controller (irrigation)","score":0.4568401873111725},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.35424673557281494},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.27496808767318726},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.26004523038864136},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.2583504915237427},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.23757612705230713}],"concepts":[{"id":"https://openalex.org/C119293636","wikidata":"https://www.wikidata.org/wiki/Q657480","display_name":"Spurious-free dynamic range","level":3,"score":0.9089717864990234},{"id":"https://openalex.org/C60154766","wikidata":"https://www.wikidata.org/wiki/Q2650458","display_name":"Successive approximation ADC","level":4,"score":0.8761112689971924},{"id":"https://openalex.org/C2778023540","wikidata":"https://www.wikidata.org/wiki/Q2164847","display_name":"Clock generator","level":4,"score":0.7314088344573975},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6463616490364075},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5606332421302795},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5590436458587646},{"id":"https://openalex.org/C2777271169","wikidata":"https://www.wikidata.org/wiki/Q190169","display_name":"Analog-to-digital converter","level":3,"score":0.4664169251918793},{"id":"https://openalex.org/C14781684","wikidata":"https://www.wikidata.org/wiki/Q3983320","display_name":"Settling time","level":3,"score":0.4604305624961853},{"id":"https://openalex.org/C2776310492","wikidata":"https://www.wikidata.org/wiki/Q3271420","display_name":"12-bit","level":3,"score":0.4589551091194153},{"id":"https://openalex.org/C203479927","wikidata":"https://www.wikidata.org/wiki/Q5165939","display_name":"Controller (irrigation)","level":2,"score":0.4568401873111725},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.35424673557281494},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.27496808767318726},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.26004523038864136},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.2583504915237427},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.23757612705230713},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C160030872","wikidata":"https://www.wikidata.org/wiki/Q2142864","display_name":"Step response","level":2,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C6557445","wikidata":"https://www.wikidata.org/wiki/Q173113","display_name":"Agronomy","level":1,"score":0.0},{"id":"https://openalex.org/C133731056","wikidata":"https://www.wikidata.org/wiki/Q4917288","display_name":"Control engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mwscas.2015.7282061","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2015.7282061","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8999999761581421}],"awards":[],"funders":[{"id":"https://openalex.org/F4320322999","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1976807891","https://openalex.org/W2030300946","https://openalex.org/W2035956092","https://openalex.org/W2052276427","https://openalex.org/W2117432625","https://openalex.org/W2163359472","https://openalex.org/W2464663646"],"related_works":["https://openalex.org/W2542593952","https://openalex.org/W4387941295","https://openalex.org/W2739351926","https://openalex.org/W2568520569","https://openalex.org/W3015687113","https://openalex.org/W4295789136","https://openalex.org/W3116897448","https://openalex.org/W1980428113","https://openalex.org/W2341231357","https://openalex.org/W2311845547"],"abstract_inverted_index":{"A":[0],"12-bit":[1],"20-MS/s":[2],"charge":[3],"redistribution":[4],"successive":[5],"approximation":[6],"register":[7],"analog-to-digital":[8],"converter":[9],"in":[10,17,29],"a":[11,40,73,85],"65-nm":[12],"CMOS":[13],"technology":[14],"is":[15,36,44],"presented":[16],"this":[18],"paper.":[19],"To":[20],"address":[21],"the":[22,48,53,60],"issue":[23],"of":[24,64,69,81],"long":[25],"DAC":[26],"settling":[27],"time":[28],"bit-conversion,":[30],"an":[31],"improved":[32],"internal":[33],"clock":[34],"generator":[35],"proposed.":[37],"In":[38],"addition,":[39],"novel":[41],"SAR":[42],"controller":[43],"introduced":[45],"to":[46],"minimize":[47],"critical":[49],"path":[50],"and":[51,67],"improve":[52],"conversion":[54],"speed.":[55],"Simulation":[56],"results":[57],"show":[58],"that":[59],"ADC":[61],"achieves":[62],"SNDR":[63],"69.6":[65],"dB":[66,71],"SFDR":[68],"79.9":[70],"with":[72],"9.82-MHz":[74],"sine-wave":[75],"input":[76],"while":[77],"dissipating":[78],"power":[79],"consumption":[80],"2.1":[82],"mW":[83],"from":[84],"1.2-V":[86],"supply.":[87]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}