{"id":"https://openalex.org/W2314625368","doi":"https://doi.org/10.1109/mwscas.2014.6908567","title":"Comparison of 130 nm technology 6T and 8T SRAM cell designs for Near-Threshold operation","display_name":"Comparison of 130 nm technology 6T and 8T SRAM cell designs for Near-Threshold operation","publication_year":2014,"publication_date":"2014-08-01","ids":{"openalex":"https://openalex.org/W2314625368","doi":"https://doi.org/10.1109/mwscas.2014.6908567","mag":"2314625368"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas.2014.6908567","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2014.6908567","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5036280615","display_name":"Mika Kutila","orcid":null},"institutions":[{"id":"https://openalex.org/I155660961","display_name":"University of Turku","ror":"https://ror.org/05vghhr25","country_code":"FI","type":"education","lineage":["https://openalex.org/I155660961"]}],"countries":["FI"],"is_corresponding":true,"raw_author_name":"Mika Kutila","raw_affiliation_strings":["University of Turku, Technology Research Center (TRC), Turun yliopisto, Finland"],"affiliations":[{"raw_affiliation_string":"University of Turku, Technology Research Center (TRC), Turun yliopisto, Finland","institution_ids":["https://openalex.org/I155660961"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038944203","display_name":"A. Paasio","orcid":"https://orcid.org/0000-0003-2543-7391"},"institutions":[{"id":"https://openalex.org/I155660961","display_name":"University of Turku","ror":"https://ror.org/05vghhr25","country_code":"FI","type":"education","lineage":["https://openalex.org/I155660961"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"Ari Paasio","raw_affiliation_strings":["University of Turku, Technology Research Center (TRC), Turun yliopisto, Finland"],"affiliations":[{"raw_affiliation_string":"University of Turku, Technology Research Center (TRC), Turun yliopisto, Finland","institution_ids":["https://openalex.org/I155660961"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5011732654","display_name":"Teijo Lehtonen","orcid":"https://orcid.org/0000-0002-1995-343X"},"institutions":[{"id":"https://openalex.org/I155660961","display_name":"University of Turku","ror":"https://ror.org/05vghhr25","country_code":"FI","type":"education","lineage":["https://openalex.org/I155660961"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"Teijo Lehtonen","raw_affiliation_strings":["University of Turku, Technology Research Center (TRC), Turun yliopisto, Finland"],"affiliations":[{"raw_affiliation_string":"University of Turku, Technology Research Center (TRC), Turun yliopisto, Finland","institution_ids":["https://openalex.org/I155660961"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5036280615"],"corresponding_institution_ids":["https://openalex.org/I155660961"],"apc_list":null,"apc_paid":null,"fwci":0.4187,"has_fulltext":false,"cited_by_count":24,"citation_normalized_percentile":{"value":0.70095613,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"925","last_page":"928"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.9376044273376465},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.6905022263526917},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.6801431775093079},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6020896434783936},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.5580753087997437},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.5307407975196838},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.5257288217544556},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5106373429298401},{"id":"https://openalex.org/keywords/energy-consumption","display_name":"Energy consumption","score":0.4771013855934143},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.47525617480278015},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4738098680973053},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.44711583852767944},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2775024175643921},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2645249366760254},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19589298963546753},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.09778138995170593}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.9376044273376465},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.6905022263526917},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.6801431775093079},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6020896434783936},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.5580753087997437},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.5307407975196838},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.5257288217544556},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5106373429298401},{"id":"https://openalex.org/C2780165032","wikidata":"https://www.wikidata.org/wiki/Q16869822","display_name":"Energy consumption","level":2,"score":0.4771013855934143},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.47525617480278015},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4738098680973053},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.44711583852767944},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2775024175643921},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2645249366760254},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19589298963546753},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.09778138995170593},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mwscas.2014.6908567","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2014.6908567","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8999999761581421}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1998525920","https://openalex.org/W2008762659","https://openalex.org/W2095633659","https://openalex.org/W2109451123","https://openalex.org/W2110160974","https://openalex.org/W2167448582"],"related_works":["https://openalex.org/W2118008391","https://openalex.org/W2186949690","https://openalex.org/W2133682266","https://openalex.org/W2154109900","https://openalex.org/W2497617944","https://openalex.org/W2167303720","https://openalex.org/W3019064768","https://openalex.org/W1563139915","https://openalex.org/W2109715593","https://openalex.org/W2061075966"],"abstract_inverted_index":{"Power":[0],"consumption":[1,28,72,81],"is":[2,15,113],"an":[3,135],"important":[4],"aspect":[5],"of":[6,29,35,58,62,65,82,144],"almost":[7],"any":[8],"electrical":[9],"device":[10],"design.":[11],"Near-Threshold":[12],"Computing":[13],"(NTC)":[14],"a":[16,50,74,117],"voltage":[17],"scaling":[18],"technique":[19],"that":[20],"makes":[21],"it":[22],"possible":[23],"to":[24,43,100,126],"reduce":[25],"the":[26,33,78,83,140],"power":[27,59,71,80,160],"CMOS":[30],"devices":[31],"with":[32,134],"cost":[34],"speed":[36],"and":[37,60,67,91,158],"reliability.":[38],"We":[39],"are":[40,96],"using":[41],"NTC":[42,109],"design":[44,127],"low-power":[45],"cache":[46],"memory":[47,94,120],"circuit":[48],"for":[49,103,108],"low-performance":[51],"sensor-based":[52],"system.":[53,85],"Caches":[54],"consume":[55],"noteworthy":[56],"portions":[57],"area":[61,157],"this":[63,87],"kind":[64],"systems,":[66],"therefore":[68],"reducing":[69],"their":[70],"has":[73,154],"meaningful":[75],"impact":[76],"on":[77],"overall":[79],"whole":[84],"In":[86],"paper,":[88],"8T":[89,111],"SRAM":[90,93,105,112,129,147,152],"6T":[92,128,146,151],"cells":[95],"compared":[97],"in":[98],"order":[99],"establish":[101],"guidelines":[102],"choosing":[104],"cell":[106,153],"constructions":[107],"systems.":[110],"traditionally":[114],"concerned":[115],"as":[116],"more":[118],"reliable":[119],"cell,":[121],"but":[122],"we":[123],"have":[124],"managed":[125],"which":[130],"executes":[131],"read":[132,138],"operation":[133,143],"acceptable":[136],"reliability;":[137],"being":[139],"most":[141],"vulnerable":[142],"conventional":[145],"cell.":[148],"Also,":[149],"our":[150],"31%":[155],"smaller":[156,159],"consumption.":[161]},"counts_by_year":[{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":4},{"year":2020,"cited_by_count":2},{"year":2018,"cited_by_count":6},{"year":2017,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}