{"id":"https://openalex.org/W2084808296","doi":"https://doi.org/10.1109/mwscas.2014.6908464","title":"Post-silicon tuning aware wafer matching algorithm for 3d integration of ICs","display_name":"Post-silicon tuning aware wafer matching algorithm for 3d integration of ICs","publication_year":2014,"publication_date":"2014-08-01","ids":{"openalex":"https://openalex.org/W2084808296","doi":"https://doi.org/10.1109/mwscas.2014.6908464","mag":"2084808296"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas.2014.6908464","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2014.6908464","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5063023316","display_name":"Sangdo Park","orcid":"https://orcid.org/0000-0002-4594-9661"},"institutions":[{"id":"https://openalex.org/I2250650973","display_name":"Samsung (South Korea)","ror":"https://ror.org/04w3jy968","country_code":"KR","type":"company","lineage":["https://openalex.org/I2250650973"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Sangdo Park","raw_affiliation_strings":["System LSI, Samsung Electronics Co., Ltd., Korea","System LSI, Samsung Electronics Co., Ltd, Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"System LSI, Samsung Electronics Co., Ltd., Korea","institution_ids":["https://openalex.org/I2250650973"]},{"raw_affiliation_string":"System LSI, Samsung Electronics Co., Ltd, Korea","institution_ids":["https://openalex.org/I2250650973"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101736516","display_name":"Taewhan Kim","orcid":"https://orcid.org/0000-0003-2376-4970"},"institutions":[{"id":"https://openalex.org/I139264467","display_name":"Seoul National University","ror":"https://ror.org/04h9pn542","country_code":"KR","type":"education","lineage":["https://openalex.org/I139264467"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Taewhan Kim","raw_affiliation_strings":["School of Electrical Engineering and Computer Science, Seoul National University, Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical Engineering and Computer Science, Seoul National University, Korea","institution_ids":["https://openalex.org/I139264467"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.1908301,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"511","last_page":"514"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/wafer","display_name":"Wafer","score":0.8471062779426575},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.6900355219841003},{"id":"https://openalex.org/keywords/parametric-statistics","display_name":"Parametric statistics","score":0.6516783237457275},{"id":"https://openalex.org/keywords/matching","display_name":"Matching (statistics)","score":0.6280131340026855},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.5278598666191101},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5123913884162903},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5000975131988525},{"id":"https://openalex.org/keywords/yield","display_name":"Yield (engineering)","score":0.4522002041339874},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.45098504424095154},{"id":"https://openalex.org/keywords/wafer-testing","display_name":"Wafer testing","score":0.4495849609375},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4283457398414612},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.42347222566604614},{"id":"https://openalex.org/keywords/three-dimensional-integrated-circuit","display_name":"Three-dimensional integrated circuit","score":0.4197993874549866},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.31793665885925293},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.3082779049873352},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.18515193462371826},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.1679978370666504}],"concepts":[{"id":"https://openalex.org/C160671074","wikidata":"https://www.wikidata.org/wiki/Q267131","display_name":"Wafer","level":2,"score":0.8471062779426575},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.6900355219841003},{"id":"https://openalex.org/C117251300","wikidata":"https://www.wikidata.org/wiki/Q1849855","display_name":"Parametric statistics","level":2,"score":0.6516783237457275},{"id":"https://openalex.org/C165064840","wikidata":"https://www.wikidata.org/wiki/Q1321061","display_name":"Matching (statistics)","level":2,"score":0.6280131340026855},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.5278598666191101},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5123913884162903},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5000975131988525},{"id":"https://openalex.org/C134121241","wikidata":"https://www.wikidata.org/wiki/Q899301","display_name":"Yield (engineering)","level":2,"score":0.4522002041339874},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.45098504424095154},{"id":"https://openalex.org/C44445679","wikidata":"https://www.wikidata.org/wiki/Q2538844","display_name":"Wafer testing","level":3,"score":0.4495849609375},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4283457398414612},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.42347222566604614},{"id":"https://openalex.org/C59088047","wikidata":"https://www.wikidata.org/wiki/Q229370","display_name":"Three-dimensional integrated circuit","level":3,"score":0.4197993874549866},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.31793665885925293},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.3082779049873352},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.18515193462371826},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.1679978370666504},{"id":"https://openalex.org/C191897082","wikidata":"https://www.wikidata.org/wiki/Q11467","display_name":"Metallurgy","level":1,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mwscas.2014.6908464","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2014.6908464","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.5}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1988244207","https://openalex.org/W1998703092","https://openalex.org/W2053822874","https://openalex.org/W2092824166","https://openalex.org/W2097006642","https://openalex.org/W2116296320","https://openalex.org/W2146630859","https://openalex.org/W2148292324","https://openalex.org/W2161129061","https://openalex.org/W2169892331","https://openalex.org/W2222512263","https://openalex.org/W6647414042"],"related_works":["https://openalex.org/W2016970881","https://openalex.org/W2054845823","https://openalex.org/W2540312267","https://openalex.org/W2367528910","https://openalex.org/W2156694894","https://openalex.org/W2031579205","https://openalex.org/W2070188681","https://openalex.org/W2338273177","https://openalex.org/W2051928579","https://openalex.org/W2470954454"],"abstract_inverted_index":{"This":[0],"work":[1],"addresses":[2],"the":[3,18,30,46,50,111,126,135],"problem":[4],"of":[5,12,17,32,91,114],"wafer-to-wafer":[6,73],"matching":[7,21,107,129],"algorithm":[8,108,130],"for":[9],"3D":[10,34,55,115],"integration":[11],"ICs.":[13],"One":[14],"critical":[15],"limitation":[16],"traditional":[19],"wafer":[20,106,128],"methods":[22],"is":[23,80,93,123,131],"that":[24,60,125],"they":[25],"have":[26],"attempted":[27],"to":[28,109,133,140],"maximize":[29],"number":[31],"resulting":[33],"ICs":[35],"with":[36,82,119],"no":[37],"faulty":[38],"(bad)":[39],"die,":[40],"but":[41],"never":[42],"took":[43],"into":[44],"account":[45],"time":[47,63],"variation":[48,64],"between":[49,65],"individual":[51],"dies":[52,66],"in":[53],"a":[54,75,87,101],"integrated":[56],"chip.":[57],"We":[58],"show":[59],"without":[61],"considering":[62],"as":[67,69],"well":[68],"within":[70],"wafers":[71],"during":[72],"matching,":[74],"more":[76],"aggressive":[77],"post-silicon":[78,102],"tuning":[79,103],"required":[81],"increased":[83],"design":[84],"cost":[85],"or":[86],"reduced":[88],"parametric":[89,112,136],"yield":[90,113,137],"chips":[92],"resulted.":[94],"To":[95],"overcome":[96],"this":[97],"limitation,":[98],"we":[99],"propose":[100],"aware":[104],"comprehensive":[105],"improve":[110],"chips.":[116],"Through":[117],"experiments":[118],"benchmark":[120],"designs,":[121],"it":[122],"shown":[124],"proposed":[127],"able":[132],"enhance":[134],"by":[138],"up":[139],"8%.":[141]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
