{"id":"https://openalex.org/W2318589983","doi":"https://doi.org/10.1109/mwscas.2014.6908461","title":"Corrected and accurate Verilog-A for linear dopant drift model of memristors","display_name":"Corrected and accurate Verilog-A for linear dopant drift model of memristors","publication_year":2014,"publication_date":"2014-08-01","ids":{"openalex":"https://openalex.org/W2318589983","doi":"https://doi.org/10.1109/mwscas.2014.6908461","mag":"2318589983"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas.2014.6908461","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2014.6908461","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108109410","display_name":"Ahmed A. M. Emara","orcid":null},"institutions":[{"id":"https://openalex.org/I145487455","display_name":"Cairo University","ror":"https://ror.org/03q21mh05","country_code":"EG","type":"education","lineage":["https://openalex.org/I145487455"]}],"countries":["EG"],"is_corresponding":true,"raw_author_name":"Ahmed A. Emara","raw_affiliation_strings":["Department of Electronics and Electrical Communications Engineering, Cairo University, Giza, Egypt"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Electrical Communications Engineering, Cairo University, Giza, Egypt","institution_ids":["https://openalex.org/I145487455"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5001606881","display_name":"Mohamed M. Aboudina","orcid":"https://orcid.org/0000-0002-1968-9659"},"institutions":[{"id":"https://openalex.org/I145487455","display_name":"Cairo University","ror":"https://ror.org/03q21mh05","country_code":"EG","type":"education","lineage":["https://openalex.org/I145487455"]}],"countries":["EG"],"is_corresponding":false,"raw_author_name":"Mohamed M. Aboudina","raw_affiliation_strings":["Department of Electronics and Electrical Communications Engineering, Cairo University, Giza, Egypt"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Electrical Communications Engineering, Cairo University, Giza, Egypt","institution_ids":["https://openalex.org/I145487455"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5073738111","display_name":"Hossam A. H. Fahmy","orcid":null},"institutions":[{"id":"https://openalex.org/I145487455","display_name":"Cairo University","ror":"https://ror.org/03q21mh05","country_code":"EG","type":"education","lineage":["https://openalex.org/I145487455"]}],"countries":["EG"],"is_corresponding":false,"raw_author_name":"Hossam A. H. Fahmy","raw_affiliation_strings":["Department of Electronics and Electrical Communications Engineering, Cairo University, Giza, Egypt"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Electrical Communications Engineering, Cairo University, Giza, Egypt","institution_ids":["https://openalex.org/I145487455"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5108109410"],"corresponding_institution_ids":["https://openalex.org/I145487455"],"apc_list":null,"apc_paid":null,"fwci":0.8373,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.78526077,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"499","last_page":"502"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11601","display_name":"Neuroscience and Neural Engineering","score":0.9939000010490417,"subfield":{"id":"https://openalex.org/subfields/2804","display_name":"Cellular and Molecular Neuroscience"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/memristor","display_name":"Memristor","score":0.8862674236297607},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.7692179083824158},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7270740270614624},{"id":"https://openalex.org/keywords/electronic-circuit-design","display_name":"Electronic circuit design","score":0.576689600944519},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5689926147460938},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.5141911506652832},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4934009611606598},{"id":"https://openalex.org/keywords/logic-simulation","display_name":"Logic simulation","score":0.4322552978992462},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.36748993396759033},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3647349178791046},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.32240888476371765},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.23781749606132507},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.18471765518188477},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.1757010817527771},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1686134934425354},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.16506421566009521},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10186663269996643}],"concepts":[{"id":"https://openalex.org/C150072547","wikidata":"https://www.wikidata.org/wiki/Q212923","display_name":"Memristor","level":2,"score":0.8862674236297607},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.7692179083824158},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7270740270614624},{"id":"https://openalex.org/C99149447","wikidata":"https://www.wikidata.org/wiki/Q5358339","display_name":"Electronic circuit design","level":3,"score":0.576689600944519},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5689926147460938},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.5141911506652832},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4934009611606598},{"id":"https://openalex.org/C64859876","wikidata":"https://www.wikidata.org/wiki/Q173673","display_name":"Logic simulation","level":3,"score":0.4322552978992462},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.36748993396759033},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3647349178791046},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.32240888476371765},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.23781749606132507},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.18471765518188477},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.1757010817527771},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1686134934425354},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.16506421566009521},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10186663269996643}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mwscas.2014.6908461","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2014.6908461","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.5199999809265137,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W2008901850","https://openalex.org/W2045009304","https://openalex.org/W2074160691","https://openalex.org/W2112181056","https://openalex.org/W2135517727","https://openalex.org/W2162651880","https://openalex.org/W2538008199","https://openalex.org/W3098259294"],"related_works":["https://openalex.org/W2388933402","https://openalex.org/W2388515366","https://openalex.org/W1903717746","https://openalex.org/W4387024066","https://openalex.org/W3129086598","https://openalex.org/W2761297466","https://openalex.org/W566385658","https://openalex.org/W1993477016","https://openalex.org/W2385740256","https://openalex.org/W2624620506"],"abstract_inverted_index":{"There":[0],"is":[1,53,70],"an":[2],"urgent":[3],"need":[4],"to":[5],"develop":[6],"accurate":[7],"memristor":[8],"circuit":[9],"models":[10,21],"for":[11,84],"use":[12],"in":[13,27],"future":[14],"large":[15,85],"designs.":[16],"Several":[17],"Verilog-A":[18,38],"and":[19,30,40,69],"SPICE":[20],"have":[22],"been":[23],"presented":[24],"which":[25],"vary":[26],"their":[28],"accuracy":[29,43],"simulation":[31,57],"speed.":[32],"This":[33],"paper":[34],"corrects":[35],"a":[36,66],"previous":[37,74],"model":[39,80],"enhances":[41],"the":[42,61,81],"of":[44,63],"another":[45],"one.":[46],"The":[47],"results":[48,77],"show":[49],"that":[50],"our":[51,79],"proposal":[52],"stable":[54],"over":[55],"long":[56],"time,":[58],"correctly":[59],"predicts":[60],"behavior":[62],"circuits,":[64],"provides":[65],"better":[67],"accuracy,":[68],"as":[71,73],"fast":[72],"models.":[75],"These":[76],"make":[78],"best":[82],"choice":[83],"memory":[86],"or":[87],"logic":[88],"circuits":[89],"designs":[90],"using":[91],"memristors.":[92]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}