{"id":"https://openalex.org/W2103882430","doi":"https://doi.org/10.1109/mwscas.2014.6908392","title":"Yield aware inter-logic-layer communication in 3-D ICs: Early design stage recommendations","display_name":"Yield aware inter-logic-layer communication in 3-D ICs: Early design stage recommendations","publication_year":2014,"publication_date":"2014-08-01","ids":{"openalex":"https://openalex.org/W2103882430","doi":"https://doi.org/10.1109/mwscas.2014.6908392","mag":"2103882430"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas.2014.6908392","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2014.6908392","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5064387160","display_name":"W. Gul","orcid":null},"institutions":[{"id":"https://openalex.org/I929597975","display_name":"National University of Sciences and Technology","ror":"https://ror.org/03w2j5y17","country_code":"PK","type":"education","lineage":["https://openalex.org/I929597975"]}],"countries":["PK"],"is_corresponding":true,"raw_author_name":"W. Gul","raw_affiliation_strings":["School of Electrical Engineering & Computer Science, National University of Sciences & Technology (NUST), Islamabad, Pakistan","School of Electrical Engineering and Computer Science, National University of Sciences and Technology (NUST), Islamabad, Pakistan"],"affiliations":[{"raw_affiliation_string":"School of Electrical Engineering & Computer Science, National University of Sciences & Technology (NUST), Islamabad, Pakistan","institution_ids":["https://openalex.org/I929597975"]},{"raw_affiliation_string":"School of Electrical Engineering and Computer Science, National University of Sciences and Technology (NUST), Islamabad, Pakistan","institution_ids":["https://openalex.org/I929597975"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034599612","display_name":"Syed Rafay Hasan","orcid":"https://orcid.org/0000-0003-0183-8086"},"institutions":[{"id":"https://openalex.org/I63920570","display_name":"Tennessee Technological University","ror":"https://ror.org/05drmrq39","country_code":"US","type":"education","lineage":["https://openalex.org/I63920570"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. R. Hasan","raw_affiliation_strings":["Department of Electrical & Computer Engineering, Tennessee Tech University, Cookeville, TN, USA","Department of Electrical and Computer Engineering, Tennessee Tech University, Cookeville, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical & Computer Engineering, Tennessee Tech University, Cookeville, TN, USA","institution_ids":["https://openalex.org/I63920570"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Tennessee Tech University, Cookeville, USA","institution_ids":["https://openalex.org/I63920570"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5066768973","display_name":"Osman Hasan","orcid":"https://orcid.org/0000-0003-2562-2669"},"institutions":[{"id":"https://openalex.org/I929597975","display_name":"National University of Sciences and Technology","ror":"https://ror.org/03w2j5y17","country_code":"PK","type":"education","lineage":["https://openalex.org/I929597975"]}],"countries":["PK"],"is_corresponding":false,"raw_author_name":"O. Hasan","raw_affiliation_strings":["School of Electrical Engineering & Computer Science, National University of Sciences & Technology (NUST), Islamabad, Pakistan","School of Electrical Engineering and Computer Science, National University of Sciences and Technology (NUST), Islamabad, Pakistan"],"affiliations":[{"raw_affiliation_string":"School of Electrical Engineering & Computer Science, National University of Sciences & Technology (NUST), Islamabad, Pakistan","institution_ids":["https://openalex.org/I929597975"]},{"raw_affiliation_string":"School of Electrical Engineering and Computer Science, National University of Sciences and Technology (NUST), Islamabad, Pakistan","institution_ids":["https://openalex.org/I929597975"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5064387160"],"corresponding_institution_ids":["https://openalex.org/I929597975"],"apc_list":null,"apc_paid":null,"fwci":0.2093,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.61124825,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"4","issue":null,"first_page":"222","last_page":"225"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9943000078201294,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9937999844551086,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.8622637987136841},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5925303101539612},{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.4701143801212311},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.442986398935318},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.4357127547264099},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.4315303862094879},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.42842841148376465},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4073014259338379},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3460061550140381},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.33947575092315674},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.33567678928375244},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.24911850690841675},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.21992889046669006},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.11017405986785889}],"concepts":[{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.8622637987136841},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5925303101539612},{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.4701143801212311},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.442986398935318},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.4357127547264099},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.4315303862094879},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.42842841148376465},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4073014259338379},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3460061550140381},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.33947575092315674},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.33567678928375244},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.24911850690841675},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.21992889046669006},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.11017405986785889},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mwscas.2014.6908392","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2014.6908392","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1570060921","https://openalex.org/W1989014215","https://openalex.org/W2010009884","https://openalex.org/W2037181413","https://openalex.org/W2054203728","https://openalex.org/W2058504720","https://openalex.org/W2063772879","https://openalex.org/W2084691364","https://openalex.org/W2085176118","https://openalex.org/W2107304970","https://openalex.org/W2122704565","https://openalex.org/W2124414146","https://openalex.org/W2138748603","https://openalex.org/W3143398174","https://openalex.org/W4255435342","https://openalex.org/W6634212967","https://openalex.org/W6652984335","https://openalex.org/W6678284070","https://openalex.org/W6678502064"],"related_works":["https://openalex.org/W1965055688","https://openalex.org/W2134697552","https://openalex.org/W301738039","https://openalex.org/W2098419840","https://openalex.org/W1966764473","https://openalex.org/W2789349722","https://openalex.org/W1985308002","https://openalex.org/W2121963733","https://openalex.org/W1977171228","https://openalex.org/W2766377030"],"abstract_inverted_index":{"3-D":[0],"ICs":[1],"provide":[2,112],"more":[3,95,105],"logic":[4],"space":[5],"by":[6],"introducing":[7],"a":[8,45,61],"multiple":[9,22],"tier":[10],"structure.":[11],"Through":[12],"silicon":[13],"vias":[14],"(TSVs)":[15],"are":[16,26],"utilized":[17],"for":[18,77,85,118],"signal":[19],"propagation":[20],"between":[21],"tiers.":[23],"However,":[24],"TSVs":[25],"vulnerable":[27],"to":[28,32,59,127],"fracture,":[29],"which":[30],"leads":[31],"lower":[33],"yield.":[34],"This":[35],"paper":[36],"analyzes":[37],"different":[38],"yield":[39],"aware":[40],"TSV":[41,80,98],"redundancy":[42,50,66,89,99,107],"techniques":[43],"from":[44],"hardware":[46,68,83],"overhead":[47,84],"and":[48,67],"effective":[49,65,106],"perspective.":[51],"A":[52],"set":[53],"of":[54,64,72],"mathematical":[55],"relationships":[56],"is":[57,91],"derived":[58],"obtain":[60],"first-order":[62],"approximation":[63],"design":[69,115],"overhead.":[70],"One":[71],"the":[73,82,119],"results":[74,111],"indicates":[75],"that":[76],"250":[78],"inter-tier":[79],"signals,":[81],"3\u00d73":[86],"router":[87],"based":[88],"technique":[90,126],"about":[92],"3":[93],"times":[94,104],"than":[96],"1:4":[97],"technique,":[100],"while":[101],"providing":[102],"5":[103],"per":[108],"cell.":[109],"Such":[110],"an":[113],"early":[114],"stage":[116],"estimate":[117],"ASIC":[120],"designer.":[121],"We":[122],"applied":[123],"our":[124],"proposed":[125],"clock":[128],"domain":[129],"crossing":[130],"(CDC)":[131],"interfaces.":[132]},"counts_by_year":[{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
