{"id":"https://openalex.org/W2328092589","doi":"https://doi.org/10.1109/mwscas.2014.6908391","title":"Fixing power bugs at RTL stage using PSL assertions","display_name":"Fixing power bugs at RTL stage using PSL assertions","publication_year":2014,"publication_date":"2014-08-01","ids":{"openalex":"https://openalex.org/W2328092589","doi":"https://doi.org/10.1109/mwscas.2014.6908391","mag":"2328092589"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas.2014.6908391","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2014.6908391","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110492453","display_name":"Carla Purdy","orcid":null},"institutions":[{"id":"https://openalex.org/I63135867","display_name":"University of Cincinnati","ror":"https://ror.org/01e3m7079","country_code":"US","type":"education","lineage":["https://openalex.org/I63135867"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Carla Purdy","raw_affiliation_strings":["School of Electronic and Computing Systems, University of Cincinnati, Cincinnati, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electronic and Computing Systems, University of Cincinnati, Cincinnati, USA","institution_ids":["https://openalex.org/I63135867"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034904478","display_name":"Chandan Singh","orcid":"https://orcid.org/0000-0002-8059-1263"},"institutions":[{"id":"https://openalex.org/I63135867","display_name":"University of Cincinnati","ror":"https://ror.org/01e3m7079","country_code":"US","type":"education","lineage":["https://openalex.org/I63135867"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Chandan Singh","raw_affiliation_strings":["School of Electronic and Computing Systems, University of Cincinnati, Cincinnati, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electronic and Computing Systems, University of Cincinnati, Cincinnati, USA","institution_ids":["https://openalex.org/I63135867"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5024089768","display_name":"Rashna Seli","orcid":null},"institutions":[{"id":"https://openalex.org/I4210094169","display_name":"STMicroelectronics (India)","ror":"https://ror.org/00ft7bw25","country_code":"IN","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210094169"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Rashna Seli","raw_affiliation_strings":["STMicroelectronics, Greater Noida, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"STMicroelectronics, Greater Noida, India","institution_ids":["https://openalex.org/I4210094169"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.26967616,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"218","last_page":"221"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.7488313317298889},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6517214179039001},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.5583655834197998},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5369574427604675},{"id":"https://openalex.org/keywords/power-optimization","display_name":"Power optimization","score":0.5331823825836182},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.48396041989326477},{"id":"https://openalex.org/keywords/scope","display_name":"Scope (computer science)","score":0.4829818308353424},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4429875612258911},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4202178120613098},{"id":"https://openalex.org/keywords/design-process","display_name":"Design process","score":0.41835713386535645},{"id":"https://openalex.org/keywords/power-integrity","display_name":"Power integrity","score":0.41810792684555054},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3950924873352051},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20057693123817444},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.16197094321250916},{"id":"https://openalex.org/keywords/signal-integrity","display_name":"Signal integrity","score":0.1400432288646698},{"id":"https://openalex.org/keywords/work-in-process","display_name":"Work in process","score":0.13787615299224854},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.11056444048881531}],"concepts":[{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.7488313317298889},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6517214179039001},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.5583655834197998},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5369574427604675},{"id":"https://openalex.org/C168292644","wikidata":"https://www.wikidata.org/wiki/Q10860336","display_name":"Power optimization","level":4,"score":0.5331823825836182},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.48396041989326477},{"id":"https://openalex.org/C2778012447","wikidata":"https://www.wikidata.org/wiki/Q1034415","display_name":"Scope (computer science)","level":2,"score":0.4829818308353424},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4429875612258911},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4202178120613098},{"id":"https://openalex.org/C48262172","wikidata":"https://www.wikidata.org/wiki/Q16908765","display_name":"Design process","level":3,"score":0.41835713386535645},{"id":"https://openalex.org/C2777561913","wikidata":"https://www.wikidata.org/wiki/Q19599527","display_name":"Power integrity","level":4,"score":0.41810792684555054},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3950924873352051},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20057693123817444},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.16197094321250916},{"id":"https://openalex.org/C44938667","wikidata":"https://www.wikidata.org/wiki/Q4503810","display_name":"Signal integrity","level":3,"score":0.1400432288646698},{"id":"https://openalex.org/C174998907","wikidata":"https://www.wikidata.org/wiki/Q357662","display_name":"Work in process","level":2,"score":0.13787615299224854},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.11056444048881531},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mwscas.2014.6908391","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2014.6908391","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W275470402","https://openalex.org/W1582019256","https://openalex.org/W1780797915","https://openalex.org/W1797377815","https://openalex.org/W1979477023","https://openalex.org/W1994564481","https://openalex.org/W2076941902","https://openalex.org/W2150453683","https://openalex.org/W2161912977","https://openalex.org/W2171603894","https://openalex.org/W3151075922","https://openalex.org/W4239884176","https://openalex.org/W4243633019"],"related_works":["https://openalex.org/W2269990635","https://openalex.org/W2543290882","https://openalex.org/W4253195573","https://openalex.org/W2020934033","https://openalex.org/W2295153704","https://openalex.org/W1519976071","https://openalex.org/W3013057549","https://openalex.org/W2097451288","https://openalex.org/W2014223528","https://openalex.org/W2009503188"],"abstract_inverted_index":{"Power":[0],"dissipation":[1],"has":[2],"now":[3],"become":[4],"the":[5,11,24,28,61,79,98,119,128,133,147,151,158],"most":[6,40],"critical":[7],"design":[8,12,34,62,80,99,134,148],"constraint.":[9],"In":[10],"flow":[13],"of":[14,30,153],"an":[15],"SoC,":[16],"power":[17,38,51,64,75,101,116,138],"estimation":[18],"and":[19,157],"analysis":[20,117],"usually":[21],"come":[22],"into":[23],"picture":[25],"only":[26],"after":[27],"completion":[29],"RTL":[31,120],"synthesis.":[32,43],"However,":[33],"optimization":[35,65],"for":[36,63],"low":[37,137],"is":[39,71,155],"suitable":[41],"before":[42,103],"Each":[44],"decrease":[45],"in":[46,60,78,112,146],"process":[47],"geometry":[48],"makes":[49],"dynamic":[50],"targets":[52],"harder":[53],"to":[54,67,73,131],"achieve.":[55],"Also,":[56],"changes":[57],"made":[58],"later":[59],"lead":[66],"costly":[68],"re-spin.":[69],"It":[70],"better":[72],"pin-point":[74],"related":[76],"problems":[77],"as":[81,83],"early":[82,143],"possible":[84],"when":[85],"they":[86],"can":[87],"still":[88],"be":[89],"fixed.":[90],"This":[91,126],"also":[92],"reduces":[93],"risk":[94],"by":[95],"ensuring":[96],"that":[97],"meets":[100],"goals":[102],"embarking":[104],"on":[105],"its":[106],"implementation.":[107],"Our":[108],"novel":[109],"approach":[110],"presented":[111],"this":[113],"paper":[114],"introduces":[115],"at":[118,140],"stage":[121,144],"itself,":[122],"using":[123],"PSL":[124],"assertions.":[125],"enables":[127],"SoC":[129],"designer":[130],"optimize":[132],"from":[135],"a":[136,141],"perspective":[139],"very":[142],"(RTL)":[145],"flow,":[149],"where":[150],"scope":[152],"modification":[154],"maximized":[156],"cost":[159],"minimized.":[160]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}