{"id":"https://openalex.org/W2324142034","doi":"https://doi.org/10.1109/mwscas.2014.6908385","title":"Flipping-based high speed VLSI architecture for 2-D lifting DWT","display_name":"Flipping-based high speed VLSI architecture for 2-D lifting DWT","publication_year":2014,"publication_date":"2014-08-01","ids":{"openalex":"https://openalex.org/W2324142034","doi":"https://doi.org/10.1109/mwscas.2014.6908385","mag":"2324142034"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas.2014.6908385","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2014.6908385","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5055835846","display_name":"Anand D. Darji","orcid":"https://orcid.org/0000-0003-0167-3453"},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"A. D. Darji","raw_affiliation_strings":["Electrical Engineering Department, Indian Institute of Technology Bombay, Powai, Mumbai"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical Engineering Department, Indian Institute of Technology Bombay, Powai, Mumbai","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054125786","display_name":"Konale Shashikanth","orcid":null},"institutions":[{"id":"https://openalex.org/I42014448","display_name":"Sardar Vallabhbhai National Institute of Technology Surat","ror":"https://ror.org/02y394t43","country_code":"IN","type":"education","lineage":["https://openalex.org/I42014448"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Konale Shashikanth","raw_affiliation_strings":["Electronics Engineering Department, S. V. National Institute of Technology, Surat, Gujarat"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electronics Engineering Department, S. V. National Institute of Technology, Surat, Gujarat","institution_ids":["https://openalex.org/I42014448"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5086470591","display_name":"Ankur Limaye","orcid":"https://orcid.org/0000-0001-9406-2584"},"institutions":[{"id":"https://openalex.org/I42014448","display_name":"Sardar Vallabhbhai National Institute of Technology Surat","ror":"https://ror.org/02y394t43","country_code":"IN","type":"education","lineage":["https://openalex.org/I42014448"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Ankur Limaye","raw_affiliation_strings":["Sardar Vallabhbhai National Institute of Technology, Surat, Gujarat, IN"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Sardar Vallabhbhai National Institute of Technology, Surat, Gujarat, IN","institution_ids":["https://openalex.org/I42014448"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5079092830","display_name":"S. N. Merchant","orcid":"https://orcid.org/0000-0002-9119-6795"},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"S. N. Merchant","raw_affiliation_strings":["Electrical Engineering Department, Indian Institute of Technology Bombay, Powai, Mumbai"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical Engineering Department, Indian Institute of Technology Bombay, Powai, Mumbai","institution_ids":["https://openalex.org/I162827531"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112072593","display_name":"A. N. Chandorkar","orcid":null},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"A. N. Chandorkar","raw_affiliation_strings":["Electrical Engineering Department, Indian Institute of Technology Bombay, Powai, Mumbai"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical Engineering Department, Indian Institute of Technology Bombay, Powai, Mumbai","institution_ids":["https://openalex.org/I162827531"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.2485,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.48182575,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"56","issue":null,"first_page":"193","last_page":"196"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10901","display_name":"Advanced Data Compression Techniques","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9948999881744385,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.8072148561477661},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.7994051575660706},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.7912294864654541},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6815730333328247},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.6686892509460449},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.6569076180458069},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6549824476242065},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.5080056190490723},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.49483436346054077},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.42648184299468994},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3823736310005188},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.34920063614845276},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.33473682403564453},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.32504504919052124},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.21467715501785278},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12319159507751465},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09439891576766968},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.079962819814682},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.0688265860080719}],"concepts":[{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.8072148561477661},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.7994051575660706},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.7912294864654541},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6815730333328247},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.6686892509460449},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.6569076180458069},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6549824476242065},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.5080056190490723},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.49483436346054077},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.42648184299468994},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3823736310005188},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.34920063614845276},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.33473682403564453},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.32504504919052124},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.21467715501785278},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12319159507751465},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09439891576766968},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.079962819814682},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0688265860080719},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mwscas.2014.6908385","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2014.6908385","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.7900000214576721,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1974581749","https://openalex.org/W2015370045","https://openalex.org/W2041862412","https://openalex.org/W2068798641","https://openalex.org/W2098917313","https://openalex.org/W2110744857","https://openalex.org/W2130260887","https://openalex.org/W2138453916","https://openalex.org/W2157030019","https://openalex.org/W4251101141","https://openalex.org/W6683290140"],"related_works":["https://openalex.org/W2355622827","https://openalex.org/W2015155483","https://openalex.org/W3004362061","https://openalex.org/W4297665406","https://openalex.org/W2364622490","https://openalex.org/W2042515040","https://openalex.org/W2383986884","https://openalex.org/W2356141508","https://openalex.org/W2749962643","https://openalex.org/W2390807153"],"abstract_inverted_index":{"In":[0,37],"this":[1],"paper,":[2],"a":[3],"flipping-based":[4],"high":[5],"speed":[6],"VLSI":[7],"architecture":[8,69,75,91],"for":[9,78],"lifting-based":[10],"2-D":[11],"DWT":[12,68],"is":[13,34,62,76,92],"proposed.":[14],"The":[15,90],"direct":[16],"implementation":[17],"of":[18],"lifting":[19],"equation":[20],"has":[21,82],"long":[22],"critical":[23,29,54],"path":[24,55],"delay.":[25],"To":[26],"reduce":[27],"the":[28,31,38,41,53,63,73],"path,":[30],"flipping":[32,44],"structure":[33,45],"widely":[35],"used.":[36],"proposed":[39,74],"architecture,":[40],"multipliers":[42],"in":[43],"are":[46],"replaced":[47],"by":[48],"shift-and-add":[49],"algorithm.":[50],"This":[51],"reduces":[52],"delay":[56,66],"to":[57],"one":[58],"adder":[59],"(T\u03b1),":[60],"which":[61],"minimum":[64],"possible":[65],"any":[67],"can":[70],"have.":[71],"Thus,":[72],"suitable":[77],"high-speed":[79],"applications":[80],"and":[81,96],"100%":[83],"hardware":[84],"utilization":[85],"with":[86],"low":[87],"control":[88],"complexity.":[89],"described":[93],"using":[94],"VHDL":[95],"implemented":[97],"on":[98],"FPGA.":[99]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}