{"id":"https://openalex.org/W2046873293","doi":"https://doi.org/10.1109/mwscas.2014.6908365","title":"Framework of a scalable delay-insensitive asynchronous platform enabling heterogeneous concurrency","display_name":"Framework of a scalable delay-insensitive asynchronous platform enabling heterogeneous concurrency","publication_year":2014,"publication_date":"2014-08-01","ids":{"openalex":"https://openalex.org/W2046873293","doi":"https://doi.org/10.1109/mwscas.2014.6908365","mag":"2046873293"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas.2014.6908365","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2014.6908365","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5035508486","display_name":"Liang Men","orcid":"https://orcid.org/0000-0001-8478-9165"},"institutions":[{"id":"https://openalex.org/I78715868","display_name":"University of Arkansas at Fayetteville","ror":"https://ror.org/05jbt9m15","country_code":"US","type":"education","lineage":["https://openalex.org/I78715868"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Liang Men","raw_affiliation_strings":["Department of Computer Science and Computer Engineering, University of Arkansas, Fayetteville, AR, USA","Department of computer science and Computer Engineering, University of Arkansas, Fayetteville, 72701 USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Computer Engineering, University of Arkansas, Fayetteville, AR, USA","institution_ids":["https://openalex.org/I78715868"]},{"raw_affiliation_string":"Department of computer science and Computer Engineering, University of Arkansas, Fayetteville, 72701 USA","institution_ids":["https://openalex.org/I78715868"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101644887","display_name":"Jia Di","orcid":"https://orcid.org/0000-0001-7718-0220"},"institutions":[{"id":"https://openalex.org/I78715868","display_name":"University of Arkansas at Fayetteville","ror":"https://ror.org/05jbt9m15","country_code":"US","type":"education","lineage":["https://openalex.org/I78715868"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jia Di","raw_affiliation_strings":["Department of Computer Science and Computer Engineering, University of Arkansas, Fayetteville, AR, USA","Department of computer science and Computer Engineering, University of Arkansas, Fayetteville, 72701 USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Computer Engineering, University of Arkansas, Fayetteville, AR, USA","institution_ids":["https://openalex.org/I78715868"]},{"raw_affiliation_string":"Department of computer science and Computer Engineering, University of Arkansas, Fayetteville, 72701 USA","institution_ids":["https://openalex.org/I78715868"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5035508486"],"corresponding_institution_ids":["https://openalex.org/I78715868"],"apc_list":null,"apc_paid":null,"fwci":0.3065,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.58834486,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"113","last_page":"116"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8413567543029785},{"id":"https://openalex.org/keywords/handshaking","display_name":"Handshaking","score":0.7645132541656494},{"id":"https://openalex.org/keywords/datapath","display_name":"Datapath","score":0.6868740320205688},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.6707460284233093},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.591056764125824},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.5807303190231323},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5511080622673035},{"id":"https://openalex.org/keywords/concurrency","display_name":"Concurrency","score":0.5328263640403748},{"id":"https://openalex.org/keywords/correctness","display_name":"Correctness","score":0.5189509391784668},{"id":"https://openalex.org/keywords/control-logic","display_name":"Control logic","score":0.5113565325737},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.4960657060146332},{"id":"https://openalex.org/keywords/construct","display_name":"Construct (python library)","score":0.4886398911476135},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.4525049924850464},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.4468730390071869},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.413571298122406},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3944895565509796},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.3069908916950226},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.23912349343299866},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.1980779767036438},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.1804884970188141},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.11572223901748657}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8413567543029785},{"id":"https://openalex.org/C58861099","wikidata":"https://www.wikidata.org/wiki/Q548838","display_name":"Handshaking","level":2,"score":0.7645132541656494},{"id":"https://openalex.org/C2781198647","wikidata":"https://www.wikidata.org/wiki/Q1633673","display_name":"Datapath","level":2,"score":0.6868740320205688},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.6707460284233093},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.591056764125824},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.5807303190231323},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5511080622673035},{"id":"https://openalex.org/C193702766","wikidata":"https://www.wikidata.org/wiki/Q1414548","display_name":"Concurrency","level":2,"score":0.5328263640403748},{"id":"https://openalex.org/C55439883","wikidata":"https://www.wikidata.org/wiki/Q360812","display_name":"Correctness","level":2,"score":0.5189509391784668},{"id":"https://openalex.org/C2776350369","wikidata":"https://www.wikidata.org/wiki/Q843479","display_name":"Control logic","level":2,"score":0.5113565325737},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.4960657060146332},{"id":"https://openalex.org/C2780801425","wikidata":"https://www.wikidata.org/wiki/Q5164392","display_name":"Construct (python library)","level":2,"score":0.4886398911476135},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.4525049924850464},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.4468730390071869},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.413571298122406},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3944895565509796},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.3069908916950226},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.23912349343299866},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.1980779767036438},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.1804884970188141},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.11572223901748657},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mwscas.2014.6908365","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2014.6908365","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.9100000262260437,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1976222993","https://openalex.org/W2099708455","https://openalex.org/W2112835666","https://openalex.org/W2117299791","https://openalex.org/W2121297016","https://openalex.org/W2138356887","https://openalex.org/W2144848004","https://openalex.org/W2153841541","https://openalex.org/W4247264372","https://openalex.org/W4299556571"],"related_works":["https://openalex.org/W2102101196","https://openalex.org/W4210841712","https://openalex.org/W2162743530","https://openalex.org/W2138197942","https://openalex.org/W2104167653","https://openalex.org/W756703083","https://openalex.org/W1690145190","https://openalex.org/W2165601350","https://openalex.org/W2517825401","https://openalex.org/W2146502274"],"abstract_inverted_index":{"Parallel":[0],"architecture":[1],"of":[2,88],"asynchronous":[3,24],"circuits":[4],"has":[5],"great":[6],"potential":[7],"in":[8,38],"improving":[9],"throughput":[10],"while":[11],"reducing":[12],"energy":[13],"consumption.":[14],"This":[15],"paper":[16],"presents":[17],"a":[18],"parallel":[19],"platform":[20,73,91],"designed":[21],"using":[22],"delay-insensitive":[23],"logic.":[25],"Heterogeneous":[26],"data":[27,47,62],"processing":[28],"units":[29,43],"as":[30,32,92,94],"well":[31,93],"datapath":[33],"control":[34,52],"logic":[35],"are":[36,56],"integrated":[37],"the":[39,45,60,72,85,89],"platform.":[40],"All":[41],"these":[42],"share":[44],"common":[46],"I/O":[48],"and":[49,69],"external":[50],"handshaking":[51],"channels.":[53],"Asynchronous":[54],"arbiters":[55],"incorporated":[57],"to":[58,74,78],"make":[59],"cores'":[61],"requests":[63],"mutually":[64],"exclusive.":[65],"The":[66],"highly-modular":[67],"interface":[68],"delay-insensitivity":[70],"allow":[71],"be":[75],"easily":[76],"cascaded":[77,96],"construct":[79],"large":[80],"systems.":[81],"Simulation":[82],"results":[83],"indicate":[84],"functional":[86],"correctness":[87],"heterogeneous":[90],"its":[95],"structure.":[97]},"counts_by_year":[{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}