{"id":"https://openalex.org/W2094801430","doi":"https://doi.org/10.1109/mwscas.2014.6908343","title":"An asynchronous finite impulse response filter design for Digital Signal Processing circuit","display_name":"An asynchronous finite impulse response filter design for Digital Signal Processing circuit","publication_year":2014,"publication_date":"2014-08-01","ids":{"openalex":"https://openalex.org/W2094801430","doi":"https://doi.org/10.1109/mwscas.2014.6908343","mag":"2094801430"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas.2014.6908343","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2014.6908343","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5035508486","display_name":"Liang Men","orcid":"https://orcid.org/0000-0001-8478-9165"},"institutions":[{"id":"https://openalex.org/I78715868","display_name":"University of Arkansas at Fayetteville","ror":"https://ror.org/05jbt9m15","country_code":"US","type":"education","lineage":["https://openalex.org/I78715868"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Liang Men","raw_affiliation_strings":["Department of Computer Science and Computer Engineering, University of Arkansas, Fayetteville, AR, USA","Department of computer science and Computer Engineering, University of Arkansas, Fayetteville, 72701 USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Computer Engineering, University of Arkansas, Fayetteville, AR, USA","institution_ids":["https://openalex.org/I78715868"]},{"raw_affiliation_string":"Department of computer science and Computer Engineering, University of Arkansas, Fayetteville, 72701 USA","institution_ids":["https://openalex.org/I78715868"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101644887","display_name":"Jia Di","orcid":"https://orcid.org/0000-0001-7718-0220"},"institutions":[{"id":"https://openalex.org/I78715868","display_name":"University of Arkansas at Fayetteville","ror":"https://ror.org/05jbt9m15","country_code":"US","type":"education","lineage":["https://openalex.org/I78715868"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jia Di","raw_affiliation_strings":["Department of Computer Science and Computer Engineering, University of Arkansas, Fayetteville, AR, USA","Department of computer science and Computer Engineering, University of Arkansas, Fayetteville, 72701 USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Computer Engineering, University of Arkansas, Fayetteville, AR, USA","institution_ids":["https://openalex.org/I78715868"]},{"raw_affiliation_string":"Department of computer science and Computer Engineering, University of Arkansas, Fayetteville, 72701 USA","institution_ids":["https://openalex.org/I78715868"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5035508486"],"corresponding_institution_ids":["https://openalex.org/I78715868"],"apc_list":null,"apc_paid":null,"fwci":0.628,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.74336805,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/finite-impulse-response","display_name":"Finite impulse response","score":0.8197954893112183},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.746241569519043},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.7396992444992065},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7186294794082642},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.6037707328796387},{"id":"https://openalex.org/keywords/digital-filter","display_name":"Digital filter","score":0.5843167901039124},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.5475940108299255},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4940071702003479},{"id":"https://openalex.org/keywords/power\u2013delay-product","display_name":"Power\u2013delay product","score":0.4848988652229309},{"id":"https://openalex.org/keywords/retiming","display_name":"Retiming","score":0.47013363242149353},{"id":"https://openalex.org/keywords/filter","display_name":"Filter (signal processing)","score":0.46787190437316895},{"id":"https://openalex.org/keywords/infinite-impulse-response","display_name":"Infinite impulse response","score":0.45938020944595337},{"id":"https://openalex.org/keywords/signal-processing","display_name":"Signal processing","score":0.44582992792129517},{"id":"https://openalex.org/keywords/impulse-response","display_name":"Impulse response","score":0.42127418518066406},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4047025144100189},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.23493024706840515},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.20687702298164368},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.18876025080680847},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.18782097101211548},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17873123288154602},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.15645787119865417},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.12424275279045105}],"concepts":[{"id":"https://openalex.org/C198386975","wikidata":"https://www.wikidata.org/wiki/Q117785","display_name":"Finite impulse response","level":2,"score":0.8197954893112183},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.746241569519043},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.7396992444992065},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7186294794082642},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.6037707328796387},{"id":"https://openalex.org/C36390408","wikidata":"https://www.wikidata.org/wiki/Q1163067","display_name":"Digital filter","level":3,"score":0.5843167901039124},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.5475940108299255},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4940071702003479},{"id":"https://openalex.org/C2776391166","wikidata":"https://www.wikidata.org/wiki/Q7236873","display_name":"Power\u2013delay product","level":4,"score":0.4848988652229309},{"id":"https://openalex.org/C41112130","wikidata":"https://www.wikidata.org/wiki/Q2146175","display_name":"Retiming","level":2,"score":0.47013363242149353},{"id":"https://openalex.org/C106131492","wikidata":"https://www.wikidata.org/wiki/Q3072260","display_name":"Filter (signal processing)","level":2,"score":0.46787190437316895},{"id":"https://openalex.org/C183816354","wikidata":"https://www.wikidata.org/wiki/Q665617","display_name":"Infinite impulse response","level":4,"score":0.45938020944595337},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.44582992792129517},{"id":"https://openalex.org/C72279823","wikidata":"https://www.wikidata.org/wiki/Q1139726","display_name":"Impulse response","level":2,"score":0.42127418518066406},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4047025144100189},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.23493024706840515},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.20687702298164368},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.18876025080680847},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.18782097101211548},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17873123288154602},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.15645787119865417},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.12424275279045105},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mwscas.2014.6908343","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2014.6908343","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.9100000262260437}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1976222993","https://openalex.org/W1996910939","https://openalex.org/W2001030538","https://openalex.org/W2026627123","https://openalex.org/W2030638977","https://openalex.org/W2046873293","https://openalex.org/W2105298326","https://openalex.org/W2117299791","https://openalex.org/W2156114874","https://openalex.org/W2165411169","https://openalex.org/W4299556571"],"related_works":["https://openalex.org/W4296061778","https://openalex.org/W3022127712","https://openalex.org/W1600620169","https://openalex.org/W1989001772","https://openalex.org/W2096148184","https://openalex.org/W2148598428","https://openalex.org/W1519267616","https://openalex.org/W2158463352","https://openalex.org/W2751942748","https://openalex.org/W1560543670"],"abstract_inverted_index":{"The":[0,48],"clockless":[1],"feature":[2],"of":[3,42,65,88],"asynchronous":[4,36],"circuit":[5,37],"promotes":[6],"its":[7],"application":[8],"in":[9,34,92],"Digital":[10],"Signal":[11],"Processing":[12],"(DSP)":[13],"under":[14],"special":[15],"applications":[16],"such":[17],"as":[18,62,85],"ultra-low":[19],"power":[20],"and":[21,55,82],"extreme":[22],"environments.":[23],"In":[24],"this":[25],"paper,":[26],"Finite":[27],"Impulse":[28],"Response":[29],"(FIR)":[30],"filter":[31,67],"is":[32],"implemented":[33],"delay-insensitivity":[35],"using":[38,68],"the":[39,69,77,86,93],"pipeline":[40,53,89],"architecture":[41],"Multi-Threshold":[43],"NULL":[44],"Conventional":[45],"Logic":[46],"(MTNCL).":[47],"computing":[49],"units":[50],"with":[51],"different":[52],"stages":[54],"pattern":[56],"delay":[57],"shift":[58],"registers":[59],"are":[60],"integrated":[61],"4":[63],"designs":[64],"FIR":[66],"IBM":[70],"130nm":[71],"8RF":[72],"process.":[73],"Simulation":[74],"results":[75],"demonstrate":[76],"tradeoff":[78],"between":[79],"system":[80],"throughput":[81],"energy":[83],"efficiency,":[84],"number":[87],"stage":[90],"changes":[91],"circuit.":[94]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
