{"id":"https://openalex.org/W1989948476","doi":"https://doi.org/10.1109/mwscas.2013.6674833","title":"A high-level synthesis and verification tool for application specific k&lt;sup&gt;th&lt;/sup&gt; Root Processing Engine","display_name":"A high-level synthesis and verification tool for application specific k&lt;sup&gt;th&lt;/sup&gt; Root Processing Engine","publication_year":2013,"publication_date":"2013-08-01","ids":{"openalex":"https://openalex.org/W1989948476","doi":"https://doi.org/10.1109/mwscas.2013.6674833","mag":"1989948476"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas.2013.6674833","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2013.6674833","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5036196802","display_name":"Semih Aslan","orcid":"https://orcid.org/0000-0003-4500-0488"},"institutions":[{"id":"https://openalex.org/I13511017","display_name":"Texas State University","ror":"https://ror.org/05h9q1g27","country_code":"US","type":"education","lineage":["https://openalex.org/I13511017"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Semih Aslan","raw_affiliation_strings":["Electrical Engineering, Texas State University, San Marcos, Texas","Ingram School of Engineering, Texas State University , San Marcos, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical Engineering, Texas State University, San Marcos, Texas","institution_ids":["https://openalex.org/I13511017"]},{"raw_affiliation_string":"Ingram School of Engineering, Texas State University , San Marcos, TX, USA","institution_ids":["https://openalex.org/I13511017"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005484411","display_name":"Hassan Salamy","orcid":"https://orcid.org/0000-0003-1314-1702"},"institutions":[{"id":"https://openalex.org/I13511017","display_name":"Texas State University","ror":"https://ror.org/05h9q1g27","country_code":"US","type":"education","lineage":["https://openalex.org/I13511017"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hassan Salamy","raw_affiliation_strings":["Electrical Engineering, Texas State University, San Marcos, Texas","Ingram School of Engineering, Texas State University , San Marcos, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical Engineering, Texas State University, San Marcos, Texas","institution_ids":["https://openalex.org/I13511017"]},{"raw_affiliation_string":"Ingram School of Engineering, Texas State University , San Marcos, TX, USA","institution_ids":["https://openalex.org/I13511017"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5018536803","display_name":"Jafar Saniie","orcid":"https://orcid.org/0000-0002-2655-6950"},"institutions":[{"id":"https://openalex.org/I180949307","display_name":"Illinois Institute of Technology","ror":"https://ror.org/037t3ry66","country_code":"US","type":"education","lineage":["https://openalex.org/I180949307"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jafar Saniie","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Illiniois Institute of Technology, Chicago, Illiniois","Dept. of Electr. & Comput. Eng., Illiniois Inst. of Technol., Chicago, IL, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Illiniois Institute of Technology, Chicago, Illiniois","institution_ids":[]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng., Illiniois Inst. of Technol., Chicago, IL, USA","institution_ids":["https://openalex.org/I180949307"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.07081103,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"1","issue":null,"first_page":"1051","last_page":"1054"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.8748986721038818},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7084647417068481},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6345503926277161},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.5422564148902893},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.4883536994457245},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4558999240398407},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.414675235748291},{"id":"https://openalex.org/keywords/functional-verification","display_name":"Functional verification","score":0.41318485140800476},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.41128450632095337},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.394827663898468},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2986947298049927}],"concepts":[{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.8748986721038818},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7084647417068481},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6345503926277161},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.5422564148902893},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.4883536994457245},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4558999240398407},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.414675235748291},{"id":"https://openalex.org/C62460635","wikidata":"https://www.wikidata.org/wiki/Q5508853","display_name":"Functional verification","level":3,"score":0.41318485140800476},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.41128450632095337},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.394827663898468},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2986947298049927}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mwscas.2013.6674833","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2013.6674833","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1996658307","https://openalex.org/W2038878650","https://openalex.org/W2085787197","https://openalex.org/W2099662985","https://openalex.org/W2120390170","https://openalex.org/W2146584722","https://openalex.org/W2149352206","https://openalex.org/W2167294532","https://openalex.org/W2539929519","https://openalex.org/W6660269412","https://openalex.org/W6729082246"],"related_works":["https://openalex.org/W2110818533","https://openalex.org/W1917852300","https://openalex.org/W2384838054","https://openalex.org/W2139058049","https://openalex.org/W2548456620","https://openalex.org/W2376018793","https://openalex.org/W2911649771","https://openalex.org/W2169179842","https://openalex.org/W2111408175","https://openalex.org/W2614101859"],"abstract_inverted_index":{"Implementation":[0],"of":[1,18,22],"division,":[2],"square":[3,101],"root,":[4],"and":[5,8,25,34,51,59,66,74,109,141,156,165,178,197,201],"cube":[6,105],"root":[7,57,102,106],"their":[9],"inverses":[10],"at":[11],"the":[12],"hardware":[13,114],"level":[14],"creates":[15],"a":[16,45,119,127,132],"number":[17],"bottlenecks":[19],"in":[20,28,37,163],"terms":[21],"accuracy,":[23],"speed":[24],"design":[26,58,65,72,82,121,140,170,177,203],"verification":[27,60,67,142,179,196],"particular.":[29],"There":[30],"are":[31,42],"many":[32],"DSP":[33],"communication":[35],"systems":[36],"which":[38,136],"these":[39],"arithmetic":[40,88],"operations":[41,89],"used.":[43],"Therefore,":[44],"Newton-Raphson":[46],"algorithm":[47],"based,":[48],"efficient,":[49],"accurate":[50,202],"reconfigurable":[52],"k":[53,94],"<sup":[54],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[55],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">th</sup>":[56],"system":[61,68,129,193],"is":[62],"introduced.":[63],"The":[64,81,112,168,191],"generates":[69,152],"Verilog":[70,153],"HDL":[71],"code":[73,155],"required":[75],"control":[76],"signals":[77],"for":[78,86,99,103,107,145,199],"application-specific":[79],"operations.":[80],"can":[83,115,123,160,172],"be":[84,116,124,161],"used":[85,117],"multi-purpose":[87],"based":[90],"on":[91,187],"an":[92],"assigned":[93],"value,":[95],"such":[96],"as":[97,118],"division":[98],"k=1,":[100],"k=2,":[104],"k=3":[108],"so":[110],"on.":[111],"generated":[113],"standalone":[120],"or":[122,147],"implemented":[125,162,186],"into":[126],"larger":[128],"by":[130,175],"using":[131],"hand":[133],"shake":[134],"signal,":[135],"could":[137],"make":[138],"this":[139],"tool":[143,151,171],"suitable":[144],"new":[146],"ongoing":[148],"projects.":[149],"This":[150],"RTL":[154],"its":[157],"testbench":[158],"that":[159],"FPGAs":[164],"VLSI":[166],"systems.":[167],"proposed":[169],"increase":[173],"productivity":[174],"reducing":[176],"time.":[180],"Several":[181],"case":[182],"studies":[183],"have":[184],"been":[185],"Xilinx":[188],"Virtex-5":[189],"FPGAs.":[190],"designed":[192],"uses":[194],"MATLAB-based":[195],"reporting":[198],"fast":[200],"evaluation.":[204]},"counts_by_year":[{"year":2022,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
