{"id":"https://openalex.org/W2040511447","doi":"https://doi.org/10.1109/mwscas.2013.6674772","title":"Comparative analysis of double gate FinFET configurations for analog circuit design","display_name":"Comparative analysis of double gate FinFET configurations for analog circuit design","publication_year":2013,"publication_date":"2013-08-01","ids":{"openalex":"https://openalex.org/W2040511447","doi":"https://doi.org/10.1109/mwscas.2013.6674772","mag":"2040511447"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas.2013.6674772","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2013.6674772","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5065315664","display_name":"Dhruva Ghai","orcid":"https://orcid.org/0000-0002-8204-6330"},"institutions":[{"id":"https://openalex.org/I138272832","display_name":"Devi Ahilya Vishwavidyalaya","ror":"https://ror.org/05c2p1f98","country_code":"IN","type":"education","lineage":["https://openalex.org/I138272832"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Dhruva Ghai","raw_affiliation_strings":["Dept. of Electronics and Communication Engineering, Oriental University, Indore, India","Dept. of Electron. & Commun. Eng., Oriental Univ., Indore, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Electronics and Communication Engineering, Oriental University, Indore, India","institution_ids":["https://openalex.org/I138272832"]},{"raw_affiliation_string":"Dept. of Electron. & Commun. Eng., Oriental Univ., Indore, India","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070359867","display_name":"Saraju P. Mohanty","orcid":"https://orcid.org/0000-0003-2959-6541"},"institutions":[{"id":"https://openalex.org/I123534392","display_name":"University of North Texas","ror":"https://ror.org/00v97ad02","country_code":"US","type":"education","lineage":["https://openalex.org/I123534392"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Saraju P. Mohanty","raw_affiliation_strings":["Dept. of Computer Science and Engineering, University of North Texas, USA","Department of Computer Science and Engineering University of North Texas Denton, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Computer Science and Engineering, University of North Texas, USA","institution_ids":["https://openalex.org/I123534392"]},{"raw_affiliation_string":"Department of Computer Science and Engineering University of North Texas Denton, TX, USA","institution_ids":["https://openalex.org/I123534392"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5008702299","display_name":"Garima Thakral","orcid":null},"institutions":[{"id":"https://openalex.org/I138272832","display_name":"Devi Ahilya Vishwavidyalaya","ror":"https://ror.org/05c2p1f98","country_code":"IN","type":"education","lineage":["https://openalex.org/I138272832"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Garima Thakral","raw_affiliation_strings":["Dept. of Computer Science, Oriental University, Indore, India","Dept. of Comput. Sci., Oriental Univ., Indore, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Computer Science, Oriental University, Indore, India","institution_ids":["https://openalex.org/I138272832"]},{"raw_affiliation_string":"Dept. of Comput. Sci., Oriental Univ., Indore, India","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":3.2424,"has_fulltext":false,"cited_by_count":26,"citation_normalized_percentile":{"value":0.92644774,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"809","last_page":"812"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/double-gate","display_name":"Double gate","score":0.5311238765716553},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.48723283410072327},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4776693284511566},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.43862223625183105},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4238035976886749},{"id":"https://openalex.org/keywords/analogue-electronics","display_name":"Analogue electronics","score":0.41323432326316833},{"id":"https://openalex.org/keywords/mosfet","display_name":"MOSFET","score":0.40080776810646057},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.3805064558982849},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21413755416870117},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.17209121584892273},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.13510751724243164}],"concepts":[{"id":"https://openalex.org/C3019885731","wikidata":"https://www.wikidata.org/wiki/Q48087455","display_name":"Double gate","level":5,"score":0.5311238765716553},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.48723283410072327},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4776693284511566},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.43862223625183105},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4238035976886749},{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.41323432326316833},{"id":"https://openalex.org/C2778413303","wikidata":"https://www.wikidata.org/wiki/Q210793","display_name":"MOSFET","level":4,"score":0.40080776810646057},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.3805064558982849},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21413755416870117},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.17209121584892273},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.13510751724243164}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mwscas.2013.6674772","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2013.6674772","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1970755039","https://openalex.org/W2024874287","https://openalex.org/W2052145319","https://openalex.org/W2062037183","https://openalex.org/W2091893572","https://openalex.org/W2096582236","https://openalex.org/W2104781003","https://openalex.org/W2112475735","https://openalex.org/W2113766915","https://openalex.org/W2130249349","https://openalex.org/W2134162576","https://openalex.org/W2141415096","https://openalex.org/W2150368362","https://openalex.org/W2152404163","https://openalex.org/W2170542648","https://openalex.org/W4235784435"],"related_works":["https://openalex.org/W2366546511","https://openalex.org/W2143475986","https://openalex.org/W2265616871","https://openalex.org/W3145896313","https://openalex.org/W2810994613","https://openalex.org/W1928698852","https://openalex.org/W1976836277","https://openalex.org/W2183842191","https://openalex.org/W3010293313","https://openalex.org/W2007156112"],"abstract_inverted_index":{"FinFETs":[0],"are":[1,88,104],"being":[2],"adopted":[3],"as":[4],"an":[5],"alternative":[6],"to":[7,20],"nanoscale":[8],"classical":[9],"MOSFET":[10],"for":[11,37,49,90,97,110,124],"digital":[12,38],"circuits.":[13],"The":[14,93],"double-gate":[15],"(DG)":[16],"FinFET":[17,36,47,65,103,126],"gives":[18],"rise":[19],"a":[21,98],"rich":[22],"design":[23,52],"space":[24],"using":[25],"various":[26,45],"configurations":[27,48,96],"of":[28,43],"the":[29,34,41,44,50,63,81,118],"gates.":[30],"Existing":[31],"research":[32],"study":[33],"DG":[35,46,64,102,125],"design.":[39,92,129],"However,":[40],"effectiveness":[42],"analog":[51,91,128],"has":[53],"not":[54],"received":[55],"much":[56],"attention.":[57],"In":[58],"this":[59],"paper,":[60],"we":[61,121],"compare":[62],"parameters":[66],"including":[67,80],"transconductance":[68],"(gm),":[69],"output":[70],"resistance":[71],"(r0),":[72],"open-circuit":[73],"gain":[74],"(gm\u00d7":[75],"r0),":[76],"transition":[77],"frequency":[78],"(fT)":[79],"most":[82],"important":[83,89],"issue,":[84],"\u201cnanoscale":[85],"variability\u201d,":[86],"which":[87],"following":[94],"three":[95],"fully":[99],"depleted":[100],"SOI":[101],"analyzed:":[105],"shorted-gate,":[106],"independent-gate,":[107],"and":[108,114],"low-power,":[109],"both":[111],"strong":[112],"inversion":[113],"subthreshold":[115],"operations.":[116],"Using":[117],"results":[119],"obtained,":[120],"present":[122],"guidelines":[123],"based":[127]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":6},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":4},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
