{"id":"https://openalex.org/W2066115620","doi":"https://doi.org/10.1109/mwscas.2012.6292061","title":"Challenges in 3DIC implementation of a design using current CAD tools","display_name":"Challenges in 3DIC implementation of a design using current CAD tools","publication_year":2012,"publication_date":"2012-08-01","ids":{"openalex":"https://openalex.org/W2066115620","doi":"https://doi.org/10.1109/mwscas.2012.6292061","mag":"2066115620"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas.2012.6292061","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2012.6292061","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5071918425","display_name":"Gopi Neela","orcid":null},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Gopi Neela","raw_affiliation_strings":["Information Sciences Institute, University of Southern California, Marina Del Rey, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Information Sciences Institute, University of Southern California, Marina Del Rey, USA","institution_ids":["https://openalex.org/I1174212"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110567690","display_name":"Jeffrey Draper","orcid":null},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jeffrey Draper","raw_affiliation_strings":["Information Sciences Institute, University of Southern California, Marina Del Rey, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Information Sciences Institute, University of Southern California, Marina Del Rey, USA","institution_ids":["https://openalex.org/I1174212"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I1174212"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"478","last_page":"481"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9959999918937683,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9901999831199646,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6010729670524597},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5689254999160767},{"id":"https://openalex.org/keywords/cad","display_name":"CAD","score":0.5398871302604675},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.5276718735694885},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.5232160091400146},{"id":"https://openalex.org/keywords/footprint","display_name":"Footprint","score":0.5231393575668335},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.45779094099998474},{"id":"https://openalex.org/keywords/three-dimensional-integrated-circuit","display_name":"Three-dimensional integrated circuit","score":0.41738396883010864},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3931922912597656},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3314934968948364},{"id":"https://openalex.org/keywords/engineering-drawing","display_name":"Engineering drawing","score":0.26333940029144287},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2612571120262146},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10305050015449524}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6010729670524597},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5689254999160767},{"id":"https://openalex.org/C194789388","wikidata":"https://www.wikidata.org/wiki/Q17855283","display_name":"CAD","level":2,"score":0.5398871302604675},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.5276718735694885},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.5232160091400146},{"id":"https://openalex.org/C132943942","wikidata":"https://www.wikidata.org/wiki/Q2562511","display_name":"Footprint","level":2,"score":0.5231393575668335},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.45779094099998474},{"id":"https://openalex.org/C59088047","wikidata":"https://www.wikidata.org/wiki/Q229370","display_name":"Three-dimensional integrated circuit","level":3,"score":0.41738396883010864},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3931922912597656},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3314934968948364},{"id":"https://openalex.org/C199639397","wikidata":"https://www.wikidata.org/wiki/Q1788588","display_name":"Engineering drawing","level":1,"score":0.26333940029144287},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2612571120262146},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10305050015449524},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mwscas.2012.6292061","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2012.6292061","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.6499999761581421}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1987131925","https://openalex.org/W2023264348","https://openalex.org/W2046574526","https://openalex.org/W2071003187","https://openalex.org/W2103704612","https://openalex.org/W2137893918","https://openalex.org/W2143807959","https://openalex.org/W2164994305"],"related_works":["https://openalex.org/W4285224955","https://openalex.org/W3205162826","https://openalex.org/W2059530328","https://openalex.org/W2119428232","https://openalex.org/W3148440458","https://openalex.org/W2338273177","https://openalex.org/W2045647383","https://openalex.org/W2080428035","https://openalex.org/W2743305891","https://openalex.org/W3198354237"],"abstract_inverted_index":{"3D":[0,42],"chip":[1,106,116,140],"stacking":[2,96],"technology":[3,149],"has":[4,27],"been":[5,28],"gaining":[6],"traction":[7],"in":[8,19,122],"recent":[9],"years,":[10],"as":[11],"academia":[12],"and":[13,68,97,118],"industry":[14],"are":[15],"showing":[16],"greater":[17],"interest":[18],"going":[20],"vertical.":[21],"However,":[22],"most":[23],"research":[24],"so":[25],"far":[26],"limited":[29],"to":[30,34,40,133],"theoretical":[31],"analysis":[32],"due":[33],"lack":[35],"of":[36,50,61,64,88,95,101,124],"industry-standard":[37],"CAD":[38,103],"tools":[39,67],"design":[41,71,132],"chips.":[43],"In":[44],"this":[45],"paper,":[46],"a":[47,51,131],"3DIC":[48],"implementation":[49],"single":[52],"precision":[53],"floating-point":[54,126],"unit":[55,127],"is":[56,72,83,141],"discussed":[57],"with":[58],"the":[59,65,86,89,99,125,136,144,153],"aim":[60],"identifying":[62],"limitations":[63],"current":[66],"methodologies.":[69],"This":[70,105],"developed":[73],"by":[74,85,152],"modifying":[75],"an":[76],"existing":[77,102],"2D":[78],"design.":[79],"The":[80,139],"partition":[81],"criterion":[82],"inspired":[84],"architecture":[87],"design,":[90],"which":[91],"can":[92],"take":[93],"advantage":[94],"enable":[98],"use":[100],"tools.":[104],"contains":[107],"two":[108],"face-to-face":[109],"bonded":[110],"tiers.":[111],"Results":[112],"show":[113],"41.5%":[114],"reduced":[115],"footprint":[117],"3%":[119],"increased":[120],"speed,":[121],"spite":[123],"being":[128],"too":[129],"small":[130],"fully":[134],"exploit":[135],"third":[137],"dimension.":[138],"built":[142],"using":[143],"Tezzaron-Global":[145],"Foundries":[146],"130nm":[147],"process":[148],"package":[150],"provided":[151],"MOSIS":[154],"organization.":[155]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2013,"cited_by_count":6}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
