{"id":"https://openalex.org/W1984535080","doi":"https://doi.org/10.1109/mwscas.2012.6292023","title":"All-digital phased-locked loop with local passive interpolation time-to-digital converter based on a tristate inverter","display_name":"All-digital phased-locked loop with local passive interpolation time-to-digital converter based on a tristate inverter","publication_year":2012,"publication_date":"2012-08-01","ids":{"openalex":"https://openalex.org/W1984535080","doi":"https://doi.org/10.1109/mwscas.2012.6292023","mag":"1984535080"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas.2012.6292023","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2012.6292023","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5039094835","display_name":"Moon Seok Kim","orcid":"https://orcid.org/0000-0002-0972-6380"},"institutions":[{"id":"https://openalex.org/I12912129","display_name":"Northeastern University","ror":"https://ror.org/04t5xt781","country_code":"US","type":"education","lineage":["https://openalex.org/I12912129"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Moon Seok Kim","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Northeastern University, Boston, MA, USA","Dept. of Electrical and Computer Engineering, Northeastern University, Boston, Massachusetts 02115, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Northeastern University, Boston, MA, USA","institution_ids":["https://openalex.org/I12912129"]},{"raw_affiliation_string":"Dept. of Electrical and Computer Engineering, Northeastern University, Boston, Massachusetts 02115, USA","institution_ids":["https://openalex.org/I12912129"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102913838","display_name":"Yong-Bin Kim","orcid":"https://orcid.org/0000-0002-7014-5630"},"institutions":[{"id":"https://openalex.org/I12912129","display_name":"Northeastern University","ror":"https://ror.org/04t5xt781","country_code":"US","type":"education","lineage":["https://openalex.org/I12912129"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yong-Bin Kim","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Northeastern University, Boston, MA, USA","Dept. of Electrical and Computer Engineering, Northeastern University, Boston, Massachusetts 02115, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Northeastern University, Boston, MA, USA","institution_ids":["https://openalex.org/I12912129"]},{"raw_affiliation_string":"Dept. of Electrical and Computer Engineering, Northeastern University, Boston, Massachusetts 02115, USA","institution_ids":["https://openalex.org/I12912129"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5049371526","display_name":"Kyung-Ki Kim","orcid":null},"institutions":[{"id":"https://openalex.org/I9323808","display_name":"Daegu University","ror":"https://ror.org/01zqccq48","country_code":"KR","type":"education","lineage":["https://openalex.org/I9323808"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Kyung-Ki Kim","raw_affiliation_strings":["School of Electronic Engineering, Daegu University, Gyeongsan, South Korea","School of Electronic Engineering, Daegu University, Gyeongsan, South Korea#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electronic Engineering, Daegu University, Gyeongsan, South Korea","institution_ids":["https://openalex.org/I9323808"]},{"raw_affiliation_string":"School of Electronic Engineering, Daegu University, Gyeongsan, South Korea#TAB#","institution_ids":["https://openalex.org/I9323808"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.2498,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.57642484,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"326","last_page":"329"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9929999709129333,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9922999739646912,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.7197767496109009},{"id":"https://openalex.org/keywords/inverter","display_name":"Inverter","score":0.6596946716308594},{"id":"https://openalex.org/keywords/time-to-digital-converter","display_name":"Time-to-digital converter","score":0.6290429830551147},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5142304301261902},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.502828061580658},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4884554445743561},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.42521873116493225},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.32675421237945557},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2560117542743683},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.23473966121673584}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.7197767496109009},{"id":"https://openalex.org/C11190779","wikidata":"https://www.wikidata.org/wiki/Q664575","display_name":"Inverter","level":3,"score":0.6596946716308594},{"id":"https://openalex.org/C99594498","wikidata":"https://www.wikidata.org/wiki/Q2434524","display_name":"Time-to-digital converter","level":4,"score":0.6290429830551147},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5142304301261902},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.502828061580658},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4884554445743561},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.42521873116493225},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.32675421237945557},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2560117542743683},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.23473966121673584},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mwscas.2012.6292023","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2012.6292023","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8999999761581421,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1977891801","https://openalex.org/W2014849399","https://openalex.org/W2110815580","https://openalex.org/W2113319198","https://openalex.org/W2145985329","https://openalex.org/W2163268258","https://openalex.org/W2164002677","https://openalex.org/W2168483816"],"related_works":["https://openalex.org/W2121182846","https://openalex.org/W2155789024","https://openalex.org/W2315668284","https://openalex.org/W3213608175","https://openalex.org/W1994021281","https://openalex.org/W2139484866","https://openalex.org/W98453623","https://openalex.org/W2340624421","https://openalex.org/W2036880312","https://openalex.org/W2128081842"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"the":[3,9,17,20,55,66,76,97,101,109],"all-digital":[4],"phase-locked":[5],"loop":[6],"(ADPLL)":[7],"with":[8,116],"local":[10],"passive":[11],"interpolation":[12],"time-to-digital":[13],"converter":[14],"(LPI-TDC).":[15],"Unlike":[16],"conventional":[18,61,77,110],"LPI-TDC,":[19],"proposed":[21,67,80],"TDC":[22],"has":[23,54,82],"a":[24,52],"tristate":[25,48,53],"inverter":[26],"delay":[27,32,35,46],"cell":[28,36],"in":[29],"only":[30,40],"first":[31],"chain,":[33],"other":[34],"is":[37,94,103,106],"composed":[38],"of":[39,57,65,100],"normal":[41],"inverters":[42],"that":[43],"have":[44],"same":[45],"as":[47],"inverter.":[49],"LPI-TDC":[50,68],"based":[51],"advantages":[56],"higher":[58],"resolution":[59,64],"than":[60,108],"LPI-TDC.":[62,78],"The":[63,79,89],"increases":[69],"by":[70],"approximately":[71],"1.5":[72],"times":[73],"compare":[74],"to":[75,91],"ADPLL":[81,102],"been":[83],"implemented":[84],"using":[85],"0.18\u03bcm":[86],"CMOS":[87],"process.":[88],"peak":[90,92],"jitter":[93],"32.86ps,":[95],"and":[96],"power":[98,118],"consumption":[99],"25.02mW,":[104],"which":[105],"lower":[107],"ADPLL,":[111],"at":[112],"600":[113],"MHz":[114],"operation":[115],"1.8V":[117],"supply":[119],"voltage.":[120]},"counts_by_year":[{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2015,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}