{"id":"https://openalex.org/W2025327887","doi":"https://doi.org/10.1109/mwscas.2012.6291970","title":"16-Bit Clocked Adiabatic Logic (CAL) logarithmic signal processor","display_name":"16-Bit Clocked Adiabatic Logic (CAL) logarithmic signal processor","publication_year":2012,"publication_date":"2012-08-01","ids":{"openalex":"https://openalex.org/W2025327887","doi":"https://doi.org/10.1109/mwscas.2012.6291970","mag":"2025327887"},"language":"en","primary_location":{"id":"doi:10.1109/mwscas.2012.6291970","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2012.6291970","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5026205748","display_name":"G\u00fcrta\u00e7 Yemi\u015f\u00e7ioglu","orcid":"https://orcid.org/0000-0003-4198-6710"},"institutions":[{"id":"https://openalex.org/I20581793","display_name":"University of Kent","ror":"https://ror.org/00xkeyj56","country_code":"GB","type":"education","lineage":["https://openalex.org/I20581793"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Gurtac Yemiscioglu","raw_affiliation_strings":["School of Engineering and Digital Arts, University of Kent, Canterbury, Kent, UK","School of Engineering and Digital Arts, University of Kent, Canterbury CT2 7NT, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Engineering and Digital Arts, University of Kent, Canterbury, Kent, UK","institution_ids":["https://openalex.org/I20581793"]},{"raw_affiliation_string":"School of Engineering and Digital Arts, University of Kent, Canterbury CT2 7NT, UK","institution_ids":["https://openalex.org/I20581793"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100354178","display_name":"Peter Lee","orcid":"https://orcid.org/0000-0002-3898-8881"},"institutions":[{"id":"https://openalex.org/I20581793","display_name":"University of Kent","ror":"https://ror.org/00xkeyj56","country_code":"GB","type":"education","lineage":["https://openalex.org/I20581793"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Peter Lee","raw_affiliation_strings":["School of Engineering and Digital Arts, University of Kent, Canterbury, Kent, UK","School of Engineering and Digital Arts, University of Kent, Canterbury CT2 7NT, UK"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Engineering and Digital Arts, University of Kent, Canterbury, Kent, UK","institution_ids":["https://openalex.org/I20581793"]},{"raw_affiliation_string":"School of Engineering and Digital Arts, University of Kent, Canterbury CT2 7NT, UK","institution_ids":["https://openalex.org/I20581793"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I20581793"],"apc_list":null,"apc_paid":null,"fwci":0.7366,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.73824352,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"113","last_page":"116"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/logarithm","display_name":"Logarithm","score":0.7767355442047119},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.6406145691871643},{"id":"https://openalex.org/keywords/adiabatic-process","display_name":"Adiabatic process","score":0.6033118367195129},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5666232705116272},{"id":"https://openalex.org/keywords/interpolation","display_name":"Interpolation (computer graphics)","score":0.522236704826355},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.5166871547698975},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5162122845649719},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5007212162017822},{"id":"https://openalex.org/keywords/16-bit","display_name":"16-bit","score":0.44665712118148804},{"id":"https://openalex.org/keywords/adiabatic-circuit","display_name":"Adiabatic circuit","score":0.44284120202064514},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.41912731528282166},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.37720298767089844},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3551672697067261},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.3390452265739441},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.33755600452423096},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.33614611625671387},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.32835549116134644},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2618764042854309},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.22863450646400452},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15802684426307678},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.12862983345985413},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10931631922721863}],"concepts":[{"id":"https://openalex.org/C39927690","wikidata":"https://www.wikidata.org/wiki/Q11197","display_name":"Logarithm","level":2,"score":0.7767355442047119},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.6406145691871643},{"id":"https://openalex.org/C109663097","wikidata":"https://www.wikidata.org/wiki/Q182453","display_name":"Adiabatic process","level":2,"score":0.6033118367195129},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5666232705116272},{"id":"https://openalex.org/C137800194","wikidata":"https://www.wikidata.org/wiki/Q11713455","display_name":"Interpolation (computer graphics)","level":3,"score":0.522236704826355},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.5166871547698975},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5162122845649719},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5007212162017822},{"id":"https://openalex.org/C33652231","wikidata":"https://www.wikidata.org/wiki/Q194368","display_name":"16-bit","level":2,"score":0.44665712118148804},{"id":"https://openalex.org/C87606752","wikidata":"https://www.wikidata.org/wiki/Q4682637","display_name":"Adiabatic circuit","level":5,"score":0.44284120202064514},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.41912731528282166},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.37720298767089844},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3551672697067261},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.3390452265739441},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.33755600452423096},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.33614611625671387},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.32835549116134644},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2618764042854309},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.22863450646400452},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15802684426307678},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.12862983345985413},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10931631922721863},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0},{"id":"https://openalex.org/C126042441","wikidata":"https://www.wikidata.org/wiki/Q1324888","display_name":"Frame (networking)","level":2,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/mwscas.2012.6291970","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mwscas.2012.6291970","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","raw_type":"proceedings-article"},{"id":"pmh:oai:kar.kent.ac.uk:35785","is_oa":false,"landing_page_url":"https://kar.kent.ac.uk/35785/","pdf_url":null,"source":{"id":"https://openalex.org/S4377196264","display_name":"Kent Academic Repository (University of Kent)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I20581793","host_organization_name":"University of Kent","host_organization_lineage":["https://openalex.org/I20581793"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Conference or workshop item"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8999999761581421}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1970858433","https://openalex.org/W2010633183","https://openalex.org/W2010635096","https://openalex.org/W2013928912","https://openalex.org/W2108907112","https://openalex.org/W2111013824","https://openalex.org/W2123135716","https://openalex.org/W2123607016","https://openalex.org/W2149677935","https://openalex.org/W2155199871","https://openalex.org/W2217187220","https://openalex.org/W2542940887","https://openalex.org/W4230863066","https://openalex.org/W6643134783","https://openalex.org/W6676294322","https://openalex.org/W6688722734"],"related_works":["https://openalex.org/W2204879205","https://openalex.org/W2096437374","https://openalex.org/W1943174035","https://openalex.org/W1928481607","https://openalex.org/W3135165657","https://openalex.org/W1485582195","https://openalex.org/W2542337934","https://openalex.org/W436907407","https://openalex.org/W3190092001","https://openalex.org/W2080546465"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"a":[3,27],"16-bit":[4],"Logarithmic":[5],"Signal":[6,33],"Processor":[7,34],"and":[8,21,45,70],"its":[9],"implementation":[10],"using":[11,38],"Clocked":[12],"Adiabatic":[13],"Logic":[14],"(CAL).":[15],"The":[16,31],"proposed":[17],"architectures":[18],"for":[19],"Lin2Log":[20],"Log2Lin":[22],"converters":[23],"are":[24],"based":[25],"on":[26],"linear":[28],"interpolation":[29],"algorithm.":[30],"CAL-Logarithmic":[32],"has":[35],"been":[36],"designed":[37],"an":[39,47],"AMS":[40],"0.35":[41],"\u03bcm":[42,51],"CMOS":[43],"process":[44],"consumes":[46],"area":[48],"of":[49],"7.3":[50],"<sup":[52],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[53],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[54],".":[55],"Spice":[56],"simulations":[57],"have":[58,73],"shown":[59],"that":[60],"the":[61,80],"circuit":[62],"can":[63],"operate":[64],"at":[65,79],"frequencies":[66],"up":[67],"to":[68],"250MHz":[69],"energy":[71],"calculation":[72],"indicated":[74],"211.34":[75],"pJ":[76],"power":[77],"consumption":[78],"maximum":[81],"operating":[82],"frequency.":[83]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":2}],"updated_date":"2026-07-02T09:51:11.867554","created_date":"2025-10-10T00:00:00"}