{"id":"https://openalex.org/W2134539402","doi":"https://doi.org/10.1109/mtdt.2003.1222356","title":"Cost optimum embedded DRAM design by yield analysis","display_name":"Cost optimum embedded DRAM design by yield analysis","publication_year":2004,"publication_date":"2004-03-01","ids":{"openalex":"https://openalex.org/W2134539402","doi":"https://doi.org/10.1109/mtdt.2003.1222356","mag":"2134539402"},"language":"en","primary_location":{"id":"doi:10.1109/mtdt.2003.1222356","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mtdt.2003.1222356","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings the Third IEEE Workshop on Internet Applications. WIAPP 2003","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5059433542","display_name":"Y. Zenda","orcid":null},"institutions":[{"id":"https://openalex.org/I98285908","display_name":"Osaka University","ror":"https://ror.org/035t8zc32","country_code":"JP","type":"education","lineage":["https://openalex.org/I98285908"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Y. Zenda","raw_affiliation_strings":["Department .of Information Systems Engineering, Osaka University, Suita, Osaka, Japan","[Department of Information Systems Engineering, Osaka University, Suita, Japan]"],"affiliations":[{"raw_affiliation_string":"Department .of Information Systems Engineering, Osaka University, Suita, Osaka, Japan","institution_ids":["https://openalex.org/I98285908"]},{"raw_affiliation_string":"[Department of Information Systems Engineering, Osaka University, Suita, Japan]","institution_ids":["https://openalex.org/I98285908"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041722144","display_name":"Koji Nakamae","orcid":"https://orcid.org/0000-0001-9269-3868"},"institutions":[{"id":"https://openalex.org/I98285908","display_name":"Osaka University","ror":"https://ror.org/035t8zc32","country_code":"JP","type":"education","lineage":["https://openalex.org/I98285908"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"K. Nakamae","raw_affiliation_strings":["Department .of Information Systems Engineering, Osaka University, Suita, Osaka, Japan","[Department of Information Systems Engineering, Osaka University, Suita, Japan]"],"affiliations":[{"raw_affiliation_string":"Department .of Information Systems Engineering, Osaka University, Suita, Osaka, Japan","institution_ids":["https://openalex.org/I98285908"]},{"raw_affiliation_string":"[Department of Information Systems Engineering, Osaka University, Suita, Japan]","institution_ids":["https://openalex.org/I98285908"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5026665036","display_name":"Hiromu Fujioka","orcid":null},"institutions":[{"id":"https://openalex.org/I98285908","display_name":"Osaka University","ror":"https://ror.org/035t8zc32","country_code":"JP","type":"education","lineage":["https://openalex.org/I98285908"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"H. Fujioka","raw_affiliation_strings":["Department .of Information Systems Engineering, Osaka University, Suita, Osaka, Japan","[Department of Information Systems Engineering, Osaka University, Suita, Japan]"],"affiliations":[{"raw_affiliation_string":"Department .of Information Systems Engineering, Osaka University, Suita, Osaka, Japan","institution_ids":["https://openalex.org/I98285908"]},{"raw_affiliation_string":"[Department of Information Systems Engineering, Osaka University, Suita, Japan]","institution_ids":["https://openalex.org/I98285908"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5059433542"],"corresponding_institution_ids":["https://openalex.org/I98285908"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.17158302,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"20","last_page":"24"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.9664347767829895},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6822971701622009},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.6562268137931824},{"id":"https://openalex.org/keywords/macro","display_name":"Macro","score":0.5490182638168335},{"id":"https://openalex.org/keywords/wafer","display_name":"Wafer","score":0.5294983983039856},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.4875492453575134},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.4722385108470917},{"id":"https://openalex.org/keywords/reliability","display_name":"Reliability (semiconductor)","score":0.44466814398765564},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.43406301736831665},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.425322949886322},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.41279205679893494},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.39102935791015625},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3119119703769684},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2970866560935974},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.24426090717315674},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.11648085713386536},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07984143495559692}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.9664347767829895},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6822971701622009},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.6562268137931824},{"id":"https://openalex.org/C166955791","wikidata":"https://www.wikidata.org/wiki/Q629579","display_name":"Macro","level":2,"score":0.5490182638168335},{"id":"https://openalex.org/C160671074","wikidata":"https://www.wikidata.org/wiki/Q267131","display_name":"Wafer","level":2,"score":0.5294983983039856},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.4875492453575134},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.4722385108470917},{"id":"https://openalex.org/C43214815","wikidata":"https://www.wikidata.org/wiki/Q7310987","display_name":"Reliability (semiconductor)","level":3,"score":0.44466814398765564},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.43406301736831665},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.425322949886322},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.41279205679893494},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.39102935791015625},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3119119703769684},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2970866560935974},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.24426090717315674},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.11648085713386536},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07984143495559692},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mtdt.2003.1222356","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mtdt.2003.1222356","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings the Third IEEE Workshop on Internet Applications. WIAPP 2003","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W2005169193","https://openalex.org/W2044963087","https://openalex.org/W2069406659","https://openalex.org/W2101406832","https://openalex.org/W2129555080","https://openalex.org/W2146110695","https://openalex.org/W2150714491","https://openalex.org/W2171874314"],"related_works":["https://openalex.org/W3120961607","https://openalex.org/W2135100917","https://openalex.org/W2081032080","https://openalex.org/W2134733504","https://openalex.org/W2144460576","https://openalex.org/W2183559057","https://openalex.org/W8358306","https://openalex.org/W2216584887","https://openalex.org/W309165247","https://openalex.org/W2006106470"],"abstract_inverted_index":{"We":[0],"study":[1],"on":[2,78],"cost":[3,124],"optimum":[4,125],"embedded":[5,20,126],"DRAM":[6,21,32,37,41,60,127],"interconnect":[7,38],"technologies":[8,39],"by":[9],"using":[10],"a":[11,65],"simple":[12],"VLSI":[13],"particle-induced":[14],"fault":[15,24],"simulator":[16,25],"modified":[17],"for":[18],"the":[19,79,89,93,100,118,123],"macro.":[22],"The":[23,59],"is":[26,62,76],"applied":[27],"to":[28,54],"an":[29],"assumed":[30,119],"4-Mbit":[31],"macro":[33,61],"production":[34],"process":[35],"with":[36,81],"of":[40,50,71,83,95,105,112],"1/2":[42,48,103],"pitch":[43,49,91,104],"115":[44,52],"nm":[45,53,56],"and":[46,75],"ASIC":[47,102],"from":[51],"500":[55],"(peripheral":[57],"circuits).":[58],"included":[63],"in":[64],"SoC":[66],"chip":[67],"that":[68,88],"has":[69],"area":[70],"1":[72],"cm/sup":[73],"2/":[74],"manufactured":[77,96],"wafer":[80,116],"size":[82],"8":[84],"inches.":[85],"Result":[86],"shows":[87],"wider":[90],"decreases":[92],"count":[94,111],"chips":[97,114],"but":[98],"increases":[99],"yield.":[101],"0.4":[106],"/spl":[107],"mu/m":[108],"achieved":[109],"maximum":[110],"good":[113],"per":[115],"under":[117],"conditions.":[120],"There":[121],"exists":[122],"design.":[128]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}