{"id":"https://openalex.org/W4256002266","doi":"https://doi.org/10.1109/mtdt.2002.1029766","title":"A simulator for evaluating redundancy analysis algorithms of repairable embedded memories","display_name":"A simulator for evaluating redundancy analysis algorithms of repairable embedded memories","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W4256002266","doi":"https://doi.org/10.1109/mtdt.2002.1029766"},"language":"en","primary_location":{"id":"doi:10.1109/mtdt.2002.1029766","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mtdt.2002.1029766","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051484648","display_name":"Rei-Fu Huang","orcid":null},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Rei-Fu Huang","raw_affiliation_strings":["Laboratory for Reliable Computing (LARC), Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Laboratory for Reliable Computing (LARC), Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100741020","display_name":"Jin-Fu Li","orcid":"https://orcid.org/0000-0003-1961-9674"},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Jin-Fu Li","raw_affiliation_strings":["Laboratory for Reliable Computing (LARC), Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Laboratory for Reliable Computing (LARC), Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111933987","display_name":"Jen-Chieh Yeh","orcid":null},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Jen-Chieh Yeh","raw_affiliation_strings":["Laboratory for Reliable Computing (LARC), Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Laboratory for Reliable Computing (LARC), Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5075548524","display_name":"Cheng\u2010Wen Wu","orcid":"https://orcid.org/0000-0001-8614-7908"},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Cheng-Wen Wu","raw_affiliation_strings":["Laboratory for Reliable Computing (LARC), Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Laboratory for Reliable Computing (LARC), Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5051484648"],"corresponding_institution_ids":["https://openalex.org/I25846049"],"apc_list":null,"apc_paid":null,"fwci":3.0185,"has_fulltext":false,"cited_by_count":28,"citation_normalized_percentile":{"value":0.91777886,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"68","last_page":"73"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9968000054359436,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.8712613582611084},{"id":"https://openalex.org/keywords/spare-part","display_name":"Spare part","score":0.7484356164932251},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6722465753555298},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4827291667461395},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3430235981941223},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2023058831691742},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.11939960718154907}],"concepts":[{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.8712613582611084},{"id":"https://openalex.org/C194648553","wikidata":"https://www.wikidata.org/wiki/Q1364774","display_name":"Spare part","level":2,"score":0.7484356164932251},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6722465753555298},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4827291667461395},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3430235981941223},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2023058831691742},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.11939960718154907},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mtdt.2002.1029766","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mtdt.2002.1029766","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1595368737","https://openalex.org/W1633725890","https://openalex.org/W1922918362","https://openalex.org/W2040066907","https://openalex.org/W2096018418","https://openalex.org/W2098987953","https://openalex.org/W2106935654","https://openalex.org/W2133058970","https://openalex.org/W2157130998","https://openalex.org/W2157571503","https://openalex.org/W2159103279","https://openalex.org/W6683403585"],"related_works":["https://openalex.org/W4391375266","https://openalex.org/W2748952813","https://openalex.org/W2376859990","https://openalex.org/W2912704652","https://openalex.org/W2381161177","https://openalex.org/W2319226115","https://openalex.org/W830772239","https://openalex.org/W2970750595","https://openalex.org/W2344117897","https://openalex.org/W2053409898"],"abstract_inverted_index":{"We":[0],"present":[1],"a":[2],"simulator":[3,12,82],"for":[4,74],"evaluating":[5],"the":[6,15,21,27,33,38,46,48,56,63,91,94,98,102,105],"redundancy":[7,43,65],"analysis":[8,66,106],"(RA)":[9],"algorithms.":[10],"The":[11,81],"can":[13,51,89],"calculate":[14],"repair":[16],"rate":[17],"(the":[18],"ratio":[19],"of":[20,23,29,32,78,93,104],"number":[22,28],"repaired":[24],"memories":[25],"to":[26],"defective":[30],"memories)":[31],"given":[34],"RA":[35],"algorithm":[36],"and":[37,42,54,60,69],"associated":[39],"memory":[40],"configuration":[41],"structure.":[44],"With":[45],"tool,":[47],"user":[49],"also":[50],"easily":[52],"assess":[53],"plan":[55],"redundant":[57],"(spare)":[58],"elements,":[59],"subsequently":[61],"develop":[62],"built-in":[64,75],"(BIRA)":[67],"algorithms":[68],"circuits":[70],"that":[71],"are":[72],"essential":[73],"self-repair":[76],"(BISR)":[77],"embedded":[79],"memories.":[80],"has":[83],"another":[84],"important":[85],"feature":[86],"-":[87],"it":[88],"simulate":[90],"sequence":[92],"detected":[95],"faults":[96],"in":[97],"real":[99],"order,":[100],"improving":[101],"accuracy":[103],"results.":[107]},"counts_by_year":[{"year":2021,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}