{"id":"https://openalex.org/W4234025235","doi":"https://doi.org/10.1109/mtdt.2002.1029757","title":"A BIST-based solution for the diagnosis of embedded memories adopting image processing techniques","display_name":"A BIST-based solution for the diagnosis of embedded memories adopting image processing techniques","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W4234025235","doi":"https://doi.org/10.1109/mtdt.2002.1029757"},"language":"en","primary_location":{"id":"doi:10.1109/mtdt.2002.1029757","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mtdt.2002.1029757","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5034801483","display_name":"D. Appello","orcid":null},"institutions":[{"id":"https://openalex.org/I4210154781","display_name":"STMicroelectronics (Italy)","ror":"https://ror.org/053bqv655","country_code":"IT","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210154781"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"D. Appello","raw_affiliation_strings":["STMicroelectronics, Cornaredo, Italy"],"affiliations":[{"raw_affiliation_string":"STMicroelectronics, Cornaredo, Italy","institution_ids":["https://openalex.org/I4210154781"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084021125","display_name":"A. Fudoli","orcid":null},"institutions":[{"id":"https://openalex.org/I4210154781","display_name":"STMicroelectronics (Italy)","ror":"https://ror.org/053bqv655","country_code":"IT","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210154781"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"A. Fudoli","raw_affiliation_strings":["STMicroelectronics, Cornaredo, Italy"],"affiliations":[{"raw_affiliation_string":"STMicroelectronics, Cornaredo, Italy","institution_ids":["https://openalex.org/I4210154781"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043908290","display_name":"Vincenzo Tancorre","orcid":"https://orcid.org/0000-0001-7959-0784"},"institutions":[{"id":"https://openalex.org/I4210154781","display_name":"STMicroelectronics (Italy)","ror":"https://ror.org/053bqv655","country_code":"IT","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210154781"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"V. Tancorre","raw_affiliation_strings":["STMicroelectronics, Cornaredo, Italy"],"affiliations":[{"raw_affiliation_string":"STMicroelectronics, Cornaredo, Italy","institution_ids":["https://openalex.org/I4210154781"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060173248","display_name":"F. Corno","orcid":null},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"F. Corno","raw_affiliation_strings":["Dipartimento di Automatica e Informatica, Politecnico di Turino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Automatica e Informatica, Politecnico di Turino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076102072","display_name":"Maurizio Rebaudengo","orcid":"https://orcid.org/0000-0002-7135-7694"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"M. Rebaudengo","raw_affiliation_strings":["Dipartimento di Automatica e Informatica, Politecnico di Turino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Automatica e Informatica, Politecnico di Turino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5058555274","display_name":"M. Sonza Reorda","orcid":"https://orcid.org/0000-0003-2899-7669"},"institutions":[{"id":"https://openalex.org/I177477856","display_name":"Polytechnic University of Turin","ror":"https://ror.org/00bgk9508","country_code":"IT","type":"education","lineage":["https://openalex.org/I177477856"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"M.S. Reorda","raw_affiliation_strings":["Dipartimento di Automatica e Informatica, Politecnico di Turino, Torino, Italy"],"affiliations":[{"raw_affiliation_string":"Dipartimento di Automatica e Informatica, Politecnico di Turino, Torino, Italy","institution_ids":["https://openalex.org/I177477856"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5034801483"],"corresponding_institution_ids":["https://openalex.org/I4210154781"],"apc_list":null,"apc_paid":null,"fwci":0.6954,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.75206242,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"14","issue":null,"first_page":"12","last_page":"16"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12549","display_name":"Image and Object Detection Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/bitmap","display_name":"Bitmap","score":0.7191049456596375},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6407392621040344},{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.6341997981071472},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.6206141710281372},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.5453649163246155},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.523186981678009},{"id":"https://openalex.org/keywords/hough-transform","display_name":"Hough transform","score":0.4876500368118286},{"id":"https://openalex.org/keywords/fault","display_name":"Fault (geology)","score":0.4683361053466797},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.45894375443458557},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.42885276675224304},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.3726467788219452},{"id":"https://openalex.org/keywords/image","display_name":"Image (mathematics)","score":0.35922783613204956},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2657107710838318},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.23558294773101807},{"id":"https://openalex.org/keywords/database","display_name":"Database","score":0.0834234356880188}],"concepts":[{"id":"https://openalex.org/C3115412","wikidata":"https://www.wikidata.org/wiki/Q1194708","display_name":"Bitmap","level":2,"score":0.7191049456596375},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6407392621040344},{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.6341997981071472},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.6206141710281372},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.5453649163246155},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.523186981678009},{"id":"https://openalex.org/C200518788","wikidata":"https://www.wikidata.org/wiki/Q195076","display_name":"Hough transform","level":3,"score":0.4876500368118286},{"id":"https://openalex.org/C175551986","wikidata":"https://www.wikidata.org/wiki/Q47089","display_name":"Fault (geology)","level":2,"score":0.4683361053466797},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.45894375443458557},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.42885276675224304},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.3726467788219452},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.35922783613204956},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2657107710838318},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.23558294773101807},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0834234356880188},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C127313418","wikidata":"https://www.wikidata.org/wiki/Q1069","display_name":"Geology","level":0,"score":0.0},{"id":"https://openalex.org/C165205528","wikidata":"https://www.wikidata.org/wiki/Q83371","display_name":"Seismology","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mtdt.2002.1029757","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mtdt.2002.1029757","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W157401731","https://openalex.org/W1924406256","https://openalex.org/W2004491626","https://openalex.org/W2021130660","https://openalex.org/W2061828845","https://openalex.org/W2106237508","https://openalex.org/W2111649915","https://openalex.org/W2134822007","https://openalex.org/W2136032562","https://openalex.org/W2142661102","https://openalex.org/W2163956547","https://openalex.org/W2164333395","https://openalex.org/W2917224946","https://openalex.org/W4247060286","https://openalex.org/W6606418402","https://openalex.org/W6679523228","https://openalex.org/W6683403585","https://openalex.org/W6684094325"],"related_works":["https://openalex.org/W2350456333","https://openalex.org/W2101993108","https://openalex.org/W2356608866","https://openalex.org/W2355840328","https://openalex.org/W1975966184","https://openalex.org/W2137246017","https://openalex.org/W2364393392","https://openalex.org/W2030098947","https://openalex.org/W3126935378","https://openalex.org/W2104293897"],"abstract_inverted_index":{"This":[0],"paper":[1],"proposes":[2],"a":[3,48,61,70,120,179],"new":[4],"solution":[5,72,118],"for":[6],"the":[7,27,30,34,40,55,78,82,86,91,97,100,107,131,139,156,159,166,169],"diagnosis":[8],"of":[9,80,109,123,168,174],"faults":[10],"in":[11,172],"embedded":[12,75],"RAMs,":[13],"currently":[14],"under":[15],"evaluation":[16],"within":[17],"STMicroelectronics.":[18],"The":[19,65,116,148],"proposed":[20,117,170],"scheme":[21,102],"uses":[22],"dedicated":[23,105],"circuitry":[24],"added":[25],"to":[26,38,57,73,89,106,130,137,154,177],"BIST":[28],"selecting":[29],"failure":[31],"data,":[32,125],"and":[33,53,85,103],"ATE":[35,83,98],"test":[36,124],"program":[37],"schedule":[39],"data":[41],"extraction":[42,122],"flow.":[43],"Testing":[44],"is":[45,104,128],"possible":[46],"through":[47],"standard":[49],"IEEE":[50],"1149.1":[51],"TAP,":[52],"allows":[54,119],"access":[56],"multiple":[58],"cores":[59],"with":[60,77],"P1500":[62],"compliant":[63],"solution.":[64],"approach":[66,171],"aims":[67],"at":[68],"implementing":[69],"low-cost":[71,114],"diagnose":[74],"RAMs":[76],"goal":[79],"minimizing":[81],"costs":[84],"time":[87,175],"required":[88,176],"extract":[90],"diagnostic":[92,101,180],"information.":[93],"In":[94,135],"our":[95],"approach,":[96],"drives":[99],"classification":[108],"faults,":[110],"only,":[111],"allowing":[112],"adopting":[113],"equipment.":[115],"scalable":[121],"whose":[126],"amount":[127],"proportional":[129],"available":[132],"testing":[133],"time.":[134],"order":[136],"accelerate":[138],"fault":[140],"classification,":[141],"image":[142],"processing":[143],"techniques":[144],"have":[145],"been":[146,152],"applied":[147],"Hough":[149],"transform":[150],"has":[151],"adopted":[153],"analyze":[155],"bitmap":[157],"representing":[158],"faulty":[160],"cells.":[161],"Preliminary":[162],"experimental":[163],"results":[164],"show":[165],"advantages":[167],"terms":[173],"complete":[178],"process.":[181]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}