{"id":"https://openalex.org/W2162483449","doi":"https://doi.org/10.1109/mse.2011.5937106","title":"ZONA — An adaptable NoC-based multiprocessor addressed to education on system-on-chip design","display_name":"ZONA — An adaptable NoC-based multiprocessor addressed to education on system-on-chip design","publication_year":2011,"publication_date":"2011-06-01","ids":{"openalex":"https://openalex.org/W2162483449","doi":"https://doi.org/10.1109/mse.2011.5937106","mag":"2162483449"},"language":"en","primary_location":{"id":"doi:10.1109/mse.2011.5937106","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mse.2011.5937106","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE International Conference on Microelectronic Systems Education","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5065507627","display_name":"Ivan Saraiva Silva","orcid":"https://orcid.org/0000-0002-5705-6932"},"institutions":[{"id":"https://openalex.org/I3121799822","display_name":"Universidade Federal do Piau\u00ed","ror":"https://ror.org/00kwnx126","country_code":"BR","type":"education","lineage":["https://openalex.org/I3121799822"]}],"countries":["BR"],"is_corresponding":true,"raw_author_name":"Ivan Saraiva Silva","raw_affiliation_strings":["Department of Informatics and Statistics, Federal University of Piau\u00ed, Teresina, Brazil"],"affiliations":[{"raw_affiliation_string":"Department of Informatics and Statistics, Federal University of Piau\u00ed, Teresina, Brazil","institution_ids":["https://openalex.org/I3121799822"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034203705","display_name":"S\u00edlvio Fernandes","orcid":null},"institutions":[{"id":"https://openalex.org/I35046152","display_name":"Universidade Federal do Rio Grande do Norte","ror":"https://ror.org/04wn09761","country_code":"BR","type":"education","lineage":["https://openalex.org/I35046152"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Silvio R. Fernandes","raw_affiliation_strings":["Department of Informatics and Applied Maths, Federal University of Rio Grande do Norte, Natal, Rio Grande do Norte, Brazil"],"affiliations":[{"raw_affiliation_string":"Department of Informatics and Applied Maths, Federal University of Rio Grande do Norte, Natal, Rio Grande do Norte, Brazil","institution_ids":["https://openalex.org/I35046152"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5091596433","display_name":"Leonardo Augusto Casillo","orcid":"https://orcid.org/0000-0002-5296-2485"},"institutions":[{"id":"https://openalex.org/I84554738","display_name":"Universidade Federal Rural do Semi-\u00c1rido","ror":"https://ror.org/05x2svh05","country_code":"BR","type":"education","lineage":["https://openalex.org/I84554738"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Leonardo A. Casillo","raw_affiliation_strings":["Department of Exact Science and Natural, Federal Rural University of the Semi-Arid, Mossoro, Rio Grande do Norte, Brazil"],"affiliations":[{"raw_affiliation_string":"Department of Exact Science and Natural, Federal Rural University of the Semi-Arid, Mossoro, Rio Grande do Norte, Brazil","institution_ids":["https://openalex.org/I84554738"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5065507627"],"corresponding_institution_ids":["https://openalex.org/I3121799822"],"apc_list":null,"apc_paid":null,"fwci":0.7002,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.74640025,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"108","last_page":"111"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.7607195377349854},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7082070112228394},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6802135109901428},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.659915566444397},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6102373003959656},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.557722270488739},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.5317893028259277},{"id":"https://openalex.org/keywords/homogeneous","display_name":"Homogeneous","score":0.48645254969596863},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4385569393634796},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3768197298049927}],"concepts":[{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.7607195377349854},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7082070112228394},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6802135109901428},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.659915566444397},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6102373003959656},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.557722270488739},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.5317893028259277},{"id":"https://openalex.org/C66882249","wikidata":"https://www.wikidata.org/wiki/Q169336","display_name":"Homogeneous","level":2,"score":0.48645254969596863},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4385569393634796},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3768197298049927},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mse.2011.5937106","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mse.2011.5937106","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE International Conference on Microelectronic Systems Education","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7699999809265137,"display_name":"Quality Education","id":"https://metadata.un.org/sdg/4"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1715248483","https://openalex.org/W2033912633","https://openalex.org/W2103518090","https://openalex.org/W2112469302","https://openalex.org/W2119677480","https://openalex.org/W2122168551","https://openalex.org/W2148911285","https://openalex.org/W2152099665","https://openalex.org/W2165099691","https://openalex.org/W2169601811","https://openalex.org/W2172307690","https://openalex.org/W2757395025"],"related_works":["https://openalex.org/W3004362061","https://openalex.org/W2364622490","https://openalex.org/W2042515040","https://openalex.org/W2383986884","https://openalex.org/W2356141508","https://openalex.org/W4297665406","https://openalex.org/W2749962643","https://openalex.org/W2101296662","https://openalex.org/W2390807153","https://openalex.org/W2540211551"],"abstract_inverted_index":{"The":[0],"design":[1],"of":[2,65],"multiprocessor":[3,34],"system-on-chip":[4,8,35],"(MP-SoC),":[5],"especially":[6],"NoC-based":[7,33],"is":[9],"a":[10,28,32,37],"relatively":[11],"new":[12],"issue":[13],"not":[14],"yet":[15],"adequately":[16],"addressed":[17],"in":[18,73],"undergraduate":[19],"curricula":[20],"and":[21,53,75],"textbooks.":[22],"In":[23],"this":[24],"paper":[25],"we":[26],"propose":[27],"didactic":[29],"architecture":[30],"for":[31],"using":[36,77],"Reconfigurable":[38],"Instruction":[39],"Set":[40],"Processor":[41],"(RISP)":[42],"as":[43],"homogeneous":[44],"processing":[45],"element.":[46],"A":[47],"simple":[48],"assembly":[49],"language":[50],"was":[51,57],"designed":[52,72],"an":[54],"assembler":[55],"tool":[56],"written":[58],"aiming":[59],"to":[60],"make":[61],"simpler":[62],"the":[63,69],"development":[64],"MP-SoC":[66],"applications.":[67],"All":[68],"components":[70],"were":[71],"VHDL":[74],"prototyped":[76],"Altera":[78],"DE2":[79],"board.":[80]},"counts_by_year":[{"year":2012,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}