{"id":"https://openalex.org/W2147895518","doi":"https://doi.org/10.1109/mse.2011.5937081","title":"Advanced logic design through hands-on digital music synthesis","display_name":"Advanced logic design through hands-on digital music synthesis","publication_year":2011,"publication_date":"2011-06-01","ids":{"openalex":"https://openalex.org/W2147895518","doi":"https://doi.org/10.1109/mse.2011.5937081","mag":"2147895518"},"language":"en","primary_location":{"id":"doi:10.1109/mse.2011.5937081","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mse.2011.5937081","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE International Conference on Microelectronic Systems Education","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5088329648","display_name":"Walter J. Condley","orcid":null},"institutions":[{"id":"https://openalex.org/I185103710","display_name":"University of California, Santa Cruz","ror":"https://ror.org/03s65by71","country_code":"US","type":"education","lineage":["https://openalex.org/I185103710"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Walter Condley","raw_affiliation_strings":["Department of Computer Engineering, University of California, Santa Cruz, Santa Cruz, CA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, University of California, Santa Cruz, Santa Cruz, CA, USA","institution_ids":["https://openalex.org/I185103710"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103400800","display_name":"Andrew W. Hill","orcid":null},"institutions":[{"id":"https://openalex.org/I185103710","display_name":"University of California, Santa Cruz","ror":"https://ror.org/03s65by71","country_code":"US","type":"education","lineage":["https://openalex.org/I185103710"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Andrew W. Hill","raw_affiliation_strings":["Department of Computer Engineering, University of California, Santa Cruz, Santa Cruz, CA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, University of California, Santa Cruz, Santa Cruz, CA, USA","institution_ids":["https://openalex.org/I185103710"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5065218759","display_name":"Matthew R. Guthaus","orcid":"https://orcid.org/0000-0002-8113-4531"},"institutions":[{"id":"https://openalex.org/I185103710","display_name":"University of California, Santa Cruz","ror":"https://ror.org/03s65by71","country_code":"US","type":"education","lineage":["https://openalex.org/I185103710"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Matthew R. Guthaus","raw_affiliation_strings":["Department of Computer Engineering, University of California, Santa Cruz, Santa Cruz, CA, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, University of California, Santa Cruz, Santa Cruz, CA, USA","institution_ids":["https://openalex.org/I185103710"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5088329648"],"corresponding_institution_ids":["https://openalex.org/I185103710"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.20689858,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"17","last_page":"20"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11283","display_name":"Experimental Learning in Engineering","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2214","display_name":"Media Technology"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11283","display_name":"Experimental Learning in Engineering","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2214","display_name":"Media Technology"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9790999889373779,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13682","display_name":"Engineering Education and Pedagogy","score":0.9771000146865845,"subfield":{"id":"https://openalex.org/subfields/2216","display_name":"Architecture"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.7287443280220032},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6976473331451416},{"id":"https://openalex.org/keywords/digital-audio","display_name":"Digital audio","score":0.6044597625732422},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6026712656021118},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.46929436922073364},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.4144384562969208},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.34960711002349854},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.34478873014450073},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.34453046321868896},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.302714467048645},{"id":"https://openalex.org/keywords/audio-signal","display_name":"Audio signal","score":0.1877100169658661},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1631660759449005},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.14339622855186462},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.13162371516227722}],"concepts":[{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.7287443280220032},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6976473331451416},{"id":"https://openalex.org/C87687168","wikidata":"https://www.wikidata.org/wiki/Q173114","display_name":"Digital audio","level":4,"score":0.6044597625732422},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6026712656021118},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.46929436922073364},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.4144384562969208},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.34960711002349854},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.34478873014450073},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.34453046321868896},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.302714467048645},{"id":"https://openalex.org/C64922751","wikidata":"https://www.wikidata.org/wiki/Q4650799","display_name":"Audio signal","level":3,"score":0.1877100169658661},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1631660759449005},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.14339622855186462},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.13162371516227722},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mse.2011.5937081","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mse.2011.5937081","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE International Conference on Microelectronic Systems Education","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W2059539419","https://openalex.org/W6665282480"],"related_works":["https://openalex.org/W1748531671","https://openalex.org/W1980349267","https://openalex.org/W2140610743","https://openalex.org/W2116326546","https://openalex.org/W2097637358","https://openalex.org/W2151104031","https://openalex.org/W2765435638","https://openalex.org/W2098419840","https://openalex.org/W1966764473","https://openalex.org/W3134372534"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,28,32,38,43],"hands-on":[4,59],"advanced":[5],"logic":[6],"design":[7,23],"course":[8],"using":[9],"digital":[10,33],"music":[11],"synthesis":[12],"as":[13],"the":[14,52,69,76,81],"basis":[15],"of":[16,46,58],"all":[17],"homework":[18],"and":[19,37,49,67],"labs.":[20],"A":[21],"Verilog-based":[22],"flow":[24],"is":[25],"coupled":[26],"with":[27],"FPGA":[29],"development":[30],"board,":[31],"to":[34],"analog":[35],"converter,":[36],"small":[39],"amplifier":[40],"which":[41],"enables":[42],"complete":[44],"progression":[45],"specification,":[47],"implementation":[48],"verification":[50],"over":[51],"10":[53],"week":[54],"quarter.":[55],"The":[56],"gratification":[57],"audio":[60],"work":[61],"increases":[62],"student":[63,71],"interest,":[64],"accelerates":[65],"learning,":[66],"improved":[68],"average":[70],"success":[72],"rate":[73],"without":[74],"altering":[75],"fundamental":[77],"material":[78],"covered":[79],"in":[80],"course.":[82]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
