{"id":"https://openalex.org/W2123517754","doi":"https://doi.org/10.1109/mse.2009.5270831","title":"Project based learning experience in VHDL digital electronic circuit design","display_name":"Project based learning experience in VHDL digital electronic circuit design","publication_year":2009,"publication_date":"2009-07-01","ids":{"openalex":"https://openalex.org/W2123517754","doi":"https://doi.org/10.1109/mse.2009.5270831","mag":"2123517754"},"language":"en","primary_location":{"id":"doi:10.1109/mse.2009.5270831","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mse.2009.5270831","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Conference on Microelectronic Systems Education","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5001879681","display_name":"Felipe Machado","orcid":"https://orcid.org/0000-0001-7674-0943"},"institutions":[{"id":"https://openalex.org/I182083151","display_name":"Universidad Rey Juan Carlos","ror":"https://ror.org/01v5cv687","country_code":"ES","type":"education","lineage":["https://openalex.org/I182083151"]}],"countries":["ES"],"is_corresponding":true,"raw_author_name":"Felipe Machado","raw_affiliation_strings":["Departamento de Tecnolog\u00eda Electronica, Universidad Rey Juan Carlos de Madrid, Madrid, Spain","Departamento de Tecnolog\u00eda Electr\u00f3nica, Universidad Rey Juan Carlos, Madrid, Spain"],"affiliations":[{"raw_affiliation_string":"Departamento de Tecnolog\u00eda Electronica, Universidad Rey Juan Carlos de Madrid, Madrid, Spain","institution_ids":["https://openalex.org/I182083151"]},{"raw_affiliation_string":"Departamento de Tecnolog\u00eda Electr\u00f3nica, Universidad Rey Juan Carlos, Madrid, Spain","institution_ids":["https://openalex.org/I182083151"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000638743","display_name":"Susana Borromeo","orcid":"https://orcid.org/0000-0002-2353-2902"},"institutions":[{"id":"https://openalex.org/I182083151","display_name":"Universidad Rey Juan Carlos","ror":"https://ror.org/01v5cv687","country_code":"ES","type":"education","lineage":["https://openalex.org/I182083151"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Susana Borromeo","raw_affiliation_strings":["Departamento de Tecnolog\u00eda Electronica, Universidad Rey Juan Carlos de Madrid, Madrid, Spain","Departamento de Tecnolog\u00eda Electr\u00f3nica, Universidad Rey Juan Carlos, Madrid, Spain"],"affiliations":[{"raw_affiliation_string":"Departamento de Tecnolog\u00eda Electronica, Universidad Rey Juan Carlos de Madrid, Madrid, Spain","institution_ids":["https://openalex.org/I182083151"]},{"raw_affiliation_string":"Departamento de Tecnolog\u00eda Electr\u00f3nica, Universidad Rey Juan Carlos, Madrid, Spain","institution_ids":["https://openalex.org/I182083151"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5051945931","display_name":"Norberto Malpica","orcid":"https://orcid.org/0000-0003-4618-7459"},"institutions":[{"id":"https://openalex.org/I182083151","display_name":"Universidad Rey Juan Carlos","ror":"https://ror.org/01v5cv687","country_code":"ES","type":"education","lineage":["https://openalex.org/I182083151"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Norberto Malpica","raw_affiliation_strings":["Departamento de Tecnolog\u00eda Electronica, Universidad Rey Juan Carlos de Madrid, Madrid, Spain","Departamento de Tecnolog\u00eda Electr\u00f3nica, Universidad Rey Juan Carlos, Madrid, Spain"],"affiliations":[{"raw_affiliation_string":"Departamento de Tecnolog\u00eda Electronica, Universidad Rey Juan Carlos de Madrid, Madrid, Spain","institution_ids":["https://openalex.org/I182083151"]},{"raw_affiliation_string":"Departamento de Tecnolog\u00eda Electr\u00f3nica, Universidad Rey Juan Carlos, Madrid, Spain","institution_ids":["https://openalex.org/I182083151"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5001879681"],"corresponding_institution_ids":["https://openalex.org/I182083151"],"apc_list":null,"apc_paid":null,"fwci":1.072,"has_fulltext":false,"cited_by_count":22,"citation_normalized_percentile":{"value":0.78826313,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"49","last_page":"52"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11283","display_name":"Experimental Learning in Engineering","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/2214","display_name":"Media Technology"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9904999732971191,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.894016683101654},{"id":"https://openalex.org/keywords/electronic-circuit-design","display_name":"Electronic circuit design","score":0.8225398063659668},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.718271017074585},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.6402324438095093},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.628518283367157},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6123777627944946},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.6042233109474182},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.514248788356781},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.513347327709198},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.46925875544548035},{"id":"https://openalex.org/keywords/design-methods","display_name":"Design methods","score":0.4562268853187561},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.4393695890903473},{"id":"https://openalex.org/keywords/electronics","display_name":"Electronics","score":0.42427873611450195},{"id":"https://openalex.org/keywords/multimedia","display_name":"Multimedia","score":0.4049212336540222},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.3451598286628723},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.30650413036346436},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.19958633184432983},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16665753722190857}],"concepts":[{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.894016683101654},{"id":"https://openalex.org/C99149447","wikidata":"https://www.wikidata.org/wiki/Q5358339","display_name":"Electronic circuit design","level":3,"score":0.8225398063659668},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.718271017074585},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.6402324438095093},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.628518283367157},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6123777627944946},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6042233109474182},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.514248788356781},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.513347327709198},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.46925875544548035},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.4562268853187561},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.4393695890903473},{"id":"https://openalex.org/C138331895","wikidata":"https://www.wikidata.org/wiki/Q11650","display_name":"Electronics","level":2,"score":0.42427873611450195},{"id":"https://openalex.org/C49774154","wikidata":"https://www.wikidata.org/wiki/Q131765","display_name":"Multimedia","level":1,"score":0.4049212336540222},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.3451598286628723},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.30650413036346436},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.19958633184432983},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16665753722190857},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/mse.2009.5270831","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mse.2009.5270831","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Conference on Microelectronic Systems Education","raw_type":"proceedings-article"},{"id":"pmh:oai:dnet:burjcdigital::858953a8ca3bcac86a5e5194149c5006","is_oa":false,"landing_page_url":"http://hdl.handle.net/10115/5557","pdf_url":null,"source":{"id":"https://openalex.org/S4306402641","display_name":"LA Referencia (Red Federada de Repositorios Institucionales de Publicaciones Cient\u00edficas)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4383465926","host_organization_name":"LA Referencia","host_organization_lineage":["https://openalex.org/I4383465926"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.5899999737739563}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W2081354636","https://openalex.org/W2104291990","https://openalex.org/W2111421843","https://openalex.org/W2140457244","https://openalex.org/W2149634175","https://openalex.org/W2162505847","https://openalex.org/W2171413757","https://openalex.org/W2208243262"],"related_works":["https://openalex.org/W2353108474","https://openalex.org/W2064892006","https://openalex.org/W2375490598","https://openalex.org/W2389932690","https://openalex.org/W1598579619","https://openalex.org/W2381799735","https://openalex.org/W2130116292","https://openalex.org/W2348627481","https://openalex.org/W2765967418","https://openalex.org/W2351675930"],"abstract_inverted_index":{"In":[0],"this":[1],"paper":[2],"we":[3],"present":[4],"our":[5],"experience":[6],"in":[7,27,39],"teaching":[8],"digital":[9,35],"electronic":[10,48],"circuit":[11],"and":[12,37,72],"system":[13],"design":[14,34,47],"with":[15],"FPGAs":[16],"using":[17],"VHDL.":[18],"The":[19],"course":[20,58],"follows":[21],"a":[22,40],"project":[23],"based":[24],"learning":[25],"methodology,":[26],"which":[28],"the":[29,44,54,57],"students":[30,46],"learn":[31],"how":[32],"to":[33],"circuits":[36,49],"systems":[38,71],"practical":[41],"way.":[42],"During":[43],"course,":[45],"of":[50,56,62],"incremental":[51],"complexity.":[52],"At":[53],"end":[55],"they":[59],"are":[60],"capable":[61],"implementing":[63],"relatively":[64],"complex":[65],"projects,":[66],"such":[67],"as":[68],"image":[69],"processing":[70],"videogames.":[73]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":3}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}