{"id":"https://openalex.org/W2155325508","doi":"https://doi.org/10.1109/mse.2009.5270830","title":"From gates to embedded systems: A bottom-up approach to digital design","display_name":"From gates to embedded systems: A bottom-up approach to digital design","publication_year":2009,"publication_date":"2009-07-01","ids":{"openalex":"https://openalex.org/W2155325508","doi":"https://doi.org/10.1109/mse.2009.5270830","mag":"2155325508"},"language":"en","primary_location":{"id":"doi:10.1109/mse.2009.5270830","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mse.2009.5270830","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Conference on Microelectronic Systems Education","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5053960221","display_name":"Giuliano Donzellini","orcid":null},"institutions":[{"id":"https://openalex.org/I83816512","display_name":"University of Genoa","ror":"https://ror.org/0107c5v14","country_code":"IT","type":"education","lineage":["https://openalex.org/I83816512"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Giuliano Donzellini","raw_affiliation_strings":["Department of Biophysical and Electronic Engineering, University of Genoa, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Biophysical and Electronic Engineering, University of Genoa, Italy","institution_ids":["https://openalex.org/I83816512"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108999871","display_name":"Domenico Ponta","orcid":null},"institutions":[{"id":"https://openalex.org/I83816512","display_name":"University of Genoa","ror":"https://ror.org/0107c5v14","country_code":"IT","type":"education","lineage":["https://openalex.org/I83816512"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Domenico Ponta","raw_affiliation_strings":["Department of Biophysical and Electronic Engineering, University of Genoa, Italy"],"affiliations":[{"raw_affiliation_string":"Department of Biophysical and Electronic Engineering, University of Genoa, Italy","institution_ids":["https://openalex.org/I83816512"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5053960221"],"corresponding_institution_ids":["https://openalex.org/I83816512"],"apc_list":null,"apc_paid":null,"fwci":2.0571,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.88437546,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"38","issue":null,"first_page":"61","last_page":"64"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11283","display_name":"Experimental Learning in Engineering","score":0.9958000183105469,"subfield":{"id":"https://openalex.org/subfields/2214","display_name":"Media Technology"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interfacing","display_name":"Interfacing","score":0.8140318393707275},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7582802772521973},{"id":"https://openalex.org/keywords/simple","display_name":"Simple (philosophy)","score":0.5884286761283875},{"id":"https://openalex.org/keywords/finite-state-machine","display_name":"Finite-state machine","score":0.5596050024032593},{"id":"https://openalex.org/keywords/state","display_name":"State (computer science)","score":0.5523579120635986},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.5494822263717651},{"id":"https://openalex.org/keywords/interrupt","display_name":"Interrupt","score":0.4776134192943573},{"id":"https://openalex.org/keywords/session","display_name":"Session (web analytics)","score":0.47690296173095703},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.47180572152137756},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.4644010365009308},{"id":"https://openalex.org/keywords/microcomputer","display_name":"Microcomputer","score":0.42413315176963806},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4047640860080719},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3909918963909149},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3549124002456665},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.33857840299606323},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.25281384587287903},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.23280441761016846},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.18903741240501404},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1661885380744934},{"id":"https://openalex.org/keywords/microcontroller","display_name":"Microcontroller","score":0.12251222133636475},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.11234474182128906},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.09405213594436646},{"id":"https://openalex.org/keywords/world-wide-web","display_name":"World Wide Web","score":0.0892590880393982}],"concepts":[{"id":"https://openalex.org/C2776303644","wikidata":"https://www.wikidata.org/wiki/Q1020499","display_name":"Interfacing","level":2,"score":0.8140318393707275},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7582802772521973},{"id":"https://openalex.org/C2780586882","wikidata":"https://www.wikidata.org/wiki/Q7520643","display_name":"Simple (philosophy)","level":2,"score":0.5884286761283875},{"id":"https://openalex.org/C167822520","wikidata":"https://www.wikidata.org/wiki/Q176452","display_name":"Finite-state machine","level":2,"score":0.5596050024032593},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.5523579120635986},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.5494822263717651},{"id":"https://openalex.org/C41661131","wikidata":"https://www.wikidata.org/wiki/Q220764","display_name":"Interrupt","level":3,"score":0.4776134192943573},{"id":"https://openalex.org/C2779182362","wikidata":"https://www.wikidata.org/wiki/Q17126187","display_name":"Session (web analytics)","level":2,"score":0.47690296173095703},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.47180572152137756},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.4644010365009308},{"id":"https://openalex.org/C132090242","wikidata":"https://www.wikidata.org/wiki/Q32738","display_name":"Microcomputer","level":3,"score":0.42413315176963806},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4047640860080719},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3909918963909149},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3549124002456665},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.33857840299606323},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.25281384587287903},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.23280441761016846},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.18903741240501404},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1661885380744934},{"id":"https://openalex.org/C173018170","wikidata":"https://www.wikidata.org/wiki/Q165678","display_name":"Microcontroller","level":2,"score":0.12251222133636475},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.11234474182128906},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.09405213594436646},{"id":"https://openalex.org/C136764020","wikidata":"https://www.wikidata.org/wiki/Q466","display_name":"World Wide Web","level":1,"score":0.0892590880393982},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/mse.2009.5270830","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mse.2009.5270830","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Conference on Microelectronic Systems Education","raw_type":"proceedings-article"},{"id":"pmh:oai:iris.unige.it:11567/240349","is_oa":false,"landing_page_url":"http://hdl.handle.net/11567/240349","pdf_url":null,"source":{"id":"https://openalex.org/S4377196291","display_name":"CINECA IRIS Institutial Research Information System (University of Genoa)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I83816512","host_organization_name":"University of Genoa","host_organization_lineage":["https://openalex.org/I83816512"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W2025691702","https://openalex.org/W2043941797","https://openalex.org/W2089155985","https://openalex.org/W2097430074","https://openalex.org/W2107310644","https://openalex.org/W2983917151","https://openalex.org/W6769739624"],"related_works":["https://openalex.org/W2776504858","https://openalex.org/W2064563776","https://openalex.org/W2535130387","https://openalex.org/W2205347728","https://openalex.org/W2188166871","https://openalex.org/W2045651232","https://openalex.org/W1531819087","https://openalex.org/W2017650358","https://openalex.org/W2546296217","https://openalex.org/W3013757523"],"abstract_inverted_index":{"The":[0,88],"paper":[1,89],"presents":[2],"Deeds,":[3],"an":[4,31,91],"educational":[5],"tool":[6],"for":[7,85],"digital":[8,68],"design.":[9],"Deeds":[10,36,62],"covers":[11],"combinational":[12],"and":[13,23,107],"sequential":[14],"logic":[15,71,106],"networks,":[16],"finite":[17],"state":[18,103],"machines,":[19],"microcomputer":[20,109],"assembly":[21],"programming":[22],"interfacing.":[24],"It":[25],"provides":[26],"quasi-professional":[27],"simulation":[28],"features":[29],"with":[30,51,98,110],"extremely":[32],"simple":[33,112],"user":[34],"interface.":[35],"can":[37],"be":[38],"seen":[39],"as":[40],"a":[41,52,82,94,99,102,108,111],"learning":[42,65],"environment":[43],"based":[44],"on":[45,59],"three":[46],"simulators":[47],"integrated":[48],"together,":[49],"associated":[50],"large":[53],"repository":[54],"of":[55,66,76,93],"application":[56],"projects,":[57],"available":[58],"the":[60,64,74],"web.":[61],"supports":[63],"contemporary":[67],"design,":[69],"from":[70],"gates":[72],"to":[73,80],"basics":[75],"embedded":[77],"systems,":[78],"helping":[79],"build":[81],"solid":[83],"foundation":[84],"further":[86],"study.":[87],"contains":[90],"example":[92],"laboratory":[95],"session":[96],"dealing":[97],"system":[100],"including":[101],"machine,":[104],"standard":[105],"interrupt":[113],"controller.":[114]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2012,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
