{"id":"https://openalex.org/W4288389152","doi":"https://doi.org/10.1109/mocast54814.2022.9837752","title":"A Low-Latency Syndrome-based Deep Learning Decoder Architecture and its FPGA Implementation","display_name":"A Low-Latency Syndrome-based Deep Learning Decoder Architecture and its FPGA Implementation","publication_year":2022,"publication_date":"2022-06-08","ids":{"openalex":"https://openalex.org/W4288389152","doi":"https://doi.org/10.1109/mocast54814.2022.9837752"},"language":"en","primary_location":{"id":"doi:10.1109/mocast54814.2022.9837752","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mocast54814.2022.9837752","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 11th International Conference on Modern Circuits and Systems Technologies (MOCAST)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5054515411","display_name":"E. Kavvousanos","orcid":null},"institutions":[{"id":"https://openalex.org/I174878644","display_name":"University of Patras","ror":"https://ror.org/017wvtq80","country_code":"GR","type":"education","lineage":["https://openalex.org/I174878644"]}],"countries":["GR"],"is_corresponding":true,"raw_author_name":"E. Kavvousanos","raw_affiliation_strings":["University of Patras,Electrical and Computer Engineering Department,Greece","Electrical and Computer Engineering Department, University of Patras, Greece"],"affiliations":[{"raw_affiliation_string":"University of Patras,Electrical and Computer Engineering Department,Greece","institution_ids":["https://openalex.org/I174878644"]},{"raw_affiliation_string":"Electrical and Computer Engineering Department, University of Patras, Greece","institution_ids":["https://openalex.org/I174878644"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5021252086","display_name":"Vassilis Paliouras","orcid":"https://orcid.org/0000-0002-1414-7500"},"institutions":[{"id":"https://openalex.org/I174878644","display_name":"University of Patras","ror":"https://ror.org/017wvtq80","country_code":"GR","type":"education","lineage":["https://openalex.org/I174878644"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"V. Paliouras","raw_affiliation_strings":["University of Patras,Electrical and Computer Engineering Department,Greece","Electrical and Computer Engineering Department, University of Patras, Greece"],"affiliations":[{"raw_affiliation_string":"University of Patras,Electrical and Computer Engineering Department,Greece","institution_ids":["https://openalex.org/I174878644"]},{"raw_affiliation_string":"Electrical and Computer Engineering Department, University of Patras, Greece","institution_ids":["https://openalex.org/I174878644"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5054515411"],"corresponding_institution_ids":["https://openalex.org/I174878644"],"apc_list":null,"apc_paid":null,"fwci":0.2764,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.55654924,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11321","display_name":"Error Correcting Code Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11321","display_name":"Error Correcting Code Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11130","display_name":"Coding theory and cryptography","score":0.994700014591217,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12131","display_name":"Wireless Signal Modulation Classification","score":0.994700014591217,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8458632230758667},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7378617525100708},{"id":"https://openalex.org/keywords/quantization","display_name":"Quantization (signal processing)","score":0.5755922198295593},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.5633610486984253},{"id":"https://openalex.org/keywords/deep-learning","display_name":"Deep learning","score":0.5207950472831726},{"id":"https://openalex.org/keywords/porting","display_name":"Porting","score":0.47002172470092773},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.42958593368530273},{"id":"https://openalex.org/keywords/cluster-analysis","display_name":"Cluster analysis","score":0.422095388174057},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.38539499044418335},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3846583962440491},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.35640949010849},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3193560242652893},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.23162662982940674},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.16705989837646484}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8458632230758667},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7378617525100708},{"id":"https://openalex.org/C28855332","wikidata":"https://www.wikidata.org/wiki/Q198099","display_name":"Quantization (signal processing)","level":2,"score":0.5755922198295593},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.5633610486984253},{"id":"https://openalex.org/C108583219","wikidata":"https://www.wikidata.org/wiki/Q197536","display_name":"Deep learning","level":2,"score":0.5207950472831726},{"id":"https://openalex.org/C106251023","wikidata":"https://www.wikidata.org/wiki/Q851989","display_name":"Porting","level":3,"score":0.47002172470092773},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.42958593368530273},{"id":"https://openalex.org/C73555534","wikidata":"https://www.wikidata.org/wiki/Q622825","display_name":"Cluster analysis","level":2,"score":0.422095388174057},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.38539499044418335},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3846583962440491},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.35640949010849},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3193560242652893},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.23162662982940674},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.16705989837646484},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mocast54814.2022.9837752","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mocast54814.2022.9837752","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 11th International Conference on Modern Circuits and Systems Technologies (MOCAST)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.5099999904632568,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1522301498","https://openalex.org/W2156826724","https://openalex.org/W2285660444","https://openalex.org/W2666368276","https://openalex.org/W2764043458","https://openalex.org/W2770861014","https://openalex.org/W2915106038","https://openalex.org/W2963120184","https://openalex.org/W2963829778","https://openalex.org/W2964070430","https://openalex.org/W2989583615","https://openalex.org/W6631190155","https://openalex.org/W6745148473"],"related_works":["https://openalex.org/W2356602486","https://openalex.org/W2351992668","https://openalex.org/W2324828474","https://openalex.org/W2374315191","https://openalex.org/W2391207559","https://openalex.org/W3204400881","https://openalex.org/W3214410901","https://openalex.org/W3204296682","https://openalex.org/W3183118997","https://openalex.org/W2917767146"],"abstract_inverted_index":{"Recently,":[0],"Machine":[1],"Learning":[2,47],"has":[3],"been":[4],"considered":[5],"as":[6],"an":[7,73],"alternative":[8],"design":[9],"paradigm":[10],"for":[11,49,98],"various":[12],"communications":[13],"sub-systems.":[14],"However,":[15],"the":[16,21,27,41,44,99,103,107,114,128],"works":[17],"that":[18,127],"have":[19],"assessed":[20],"performance":[22,42],"of":[23,43,55,106,136],"these":[24],"methods":[25],"beyond":[26],"algorithmic":[28],"level":[29],"are":[30,123],"limited.":[31],"In":[32],"this":[33],"paper,":[34],"we":[35],"implement":[36],"in":[37,53,81,90,110],"hardware":[38,119],"and":[39,58,70,139],"evaluate":[40],"Syndrome-based":[45],"Deep":[46],"Decoder":[48],"a":[50,134,137,140],"BCH(63,45)":[51],"code":[52],"terms":[54],"throughput":[56,141],"rate":[57,142],"latency.":[59],"The":[60],"implemented":[61],"Neural":[62,108],"Network":[63,109],"is":[64,96],"compressed":[65,104],"by":[66,151],"applying":[67],"pruning,":[68],"clustering":[69],"quantization":[71],"to":[72,112,144],"8-bit":[74],"fixed-point":[75],"representation,":[76],"with":[77,117],"no":[78],"significant":[79],"loss":[80],"its":[82],"BER":[83],"performance,":[84],"while":[85],"achieving":[86],"90%":[87],"weight":[88],"sparsity":[89],"each":[91],"layer.":[92],"An":[93],"FPGA":[94],"architecture":[95],"designed":[97],"decoder":[100,129],"which":[101,125],"exploits":[102],"structure":[105],"order":[111],"accelerate":[113],"underlying":[115],"computations":[116],"moderate":[118],"requirements.":[120],"Experimental":[121],"results":[122],"provided":[124],"show":[126],"achieves":[130],"latency":[131],"less":[132],"than":[133],"tenth":[135],"millisecond":[138],"up":[143],"5":[145],"Mbps,":[146],"substantially":[147],"outperforming":[148],"previous":[149],"implementations":[150],"30\u00d7.":[152]},"counts_by_year":[{"year":2024,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
