{"id":"https://openalex.org/W2952817905","doi":"https://doi.org/10.1109/mocast.2019.8741782","title":"Design of a SystemVerilog-Based VCO Real Number Model","display_name":"Design of a SystemVerilog-Based VCO Real Number Model","publication_year":2019,"publication_date":"2019-05-01","ids":{"openalex":"https://openalex.org/W2952817905","doi":"https://doi.org/10.1109/mocast.2019.8741782","mag":"2952817905"},"language":"en","primary_location":{"id":"doi:10.1109/mocast.2019.8741782","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mocast.2019.8741782","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 8th International Conference on Modern Circuits and Systems Technologies (MOCAST)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5067554866","display_name":"Nikolaos Georgoulopoulos","orcid":"https://orcid.org/0000-0003-2044-4453"},"institutions":[{"id":"https://openalex.org/I21370196","display_name":"Aristotle University of Thessaloniki","ror":"https://ror.org/02j61yw88","country_code":"GR","type":"education","lineage":["https://openalex.org/I21370196"]}],"countries":["GR"],"is_corresponding":true,"raw_author_name":"Nikolaos Georgoulopoulos","raw_affiliation_strings":["Dept. of Electrical and Computer Engineering, Aristotle University of Thessaloniki, Thessaloniki, Greece"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical and Computer Engineering, Aristotle University of Thessaloniki, Thessaloniki, Greece","institution_ids":["https://openalex.org/I21370196"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022229501","display_name":"Athanasios Mekras","orcid":null},"institutions":[{"id":"https://openalex.org/I21370196","display_name":"Aristotle University of Thessaloniki","ror":"https://ror.org/02j61yw88","country_code":"GR","type":"education","lineage":["https://openalex.org/I21370196"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Athanasios Mekras","raw_affiliation_strings":["Dept. of Electrical and Computer Engineering, Aristotle University of Thessaloniki, Thessaloniki, Greece"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical and Computer Engineering, Aristotle University of Thessaloniki, Thessaloniki, Greece","institution_ids":["https://openalex.org/I21370196"]}]},{"author_position":"last","author":{"id":null,"display_name":"Alkiviadis Hatzopoulos","orcid":null},"institutions":[{"id":"https://openalex.org/I21370196","display_name":"Aristotle University of Thessaloniki","ror":"https://ror.org/02j61yw88","country_code":"GR","type":"education","lineage":["https://openalex.org/I21370196"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Alkiviadis Hatzopoulos","raw_affiliation_strings":["Dept. of Electrical and Computer Engineering, Aristotle University of Thessaloniki, Thessaloniki, Greece"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical and Computer Engineering, Aristotle University of Thessaloniki, Thessaloniki, Greece","institution_ids":["https://openalex.org/I21370196"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5067554866"],"corresponding_institution_ids":["https://openalex.org/I21370196"],"apc_list":null,"apc_paid":null,"fwci":0.0997,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.4296763,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/voltage-controlled-oscillator","display_name":"Voltage-controlled oscillator","score":0.8621728420257568},{"id":"https://openalex.org/keywords/cadence","display_name":"Cadence","score":0.8274080157279968},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.7799214124679565},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7295811176300049},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.42012789845466614},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4108276069164276},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.3674179017543793},{"id":"https://openalex.org/keywords/simulation","display_name":"Simulation","score":0.36247873306274414},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.32199734449386597},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2906109094619751},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.27012473344802856},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.11547094583511353},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.10177654027938843},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.09197932481765747}],"concepts":[{"id":"https://openalex.org/C5291336","wikidata":"https://www.wikidata.org/wiki/Q852341","display_name":"Voltage-controlled oscillator","level":3,"score":0.8621728420257568},{"id":"https://openalex.org/C2777125575","wikidata":"https://www.wikidata.org/wiki/Q14088448","display_name":"Cadence","level":2,"score":0.8274080157279968},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.7799214124679565},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7295811176300049},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.42012789845466614},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4108276069164276},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.3674179017543793},{"id":"https://openalex.org/C44154836","wikidata":"https://www.wikidata.org/wiki/Q45045","display_name":"Simulation","level":1,"score":0.36247873306274414},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.32199734449386597},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2906109094619751},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.27012473344802856},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.11547094583511353},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.10177654027938843},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.09197932481765747},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mocast.2019.8741782","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mocast.2019.8741782","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2019 8th International Conference on Modern Circuits and Systems Technologies (MOCAST)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W566385658","https://openalex.org/W1506018222","https://openalex.org/W1546370875","https://openalex.org/W1571561033","https://openalex.org/W2027634747","https://openalex.org/W2062573476","https://openalex.org/W2069063184","https://openalex.org/W2134558891","https://openalex.org/W2150521192","https://openalex.org/W2318589983","https://openalex.org/W2504287186","https://openalex.org/W2504995469","https://openalex.org/W2511968708","https://openalex.org/W2735991644","https://openalex.org/W2782738696","https://openalex.org/W2808375863","https://openalex.org/W2890757532","https://openalex.org/W2891055363","https://openalex.org/W6632762336","https://openalex.org/W6634123474"],"related_works":["https://openalex.org/W4289538008","https://openalex.org/W3186427148","https://openalex.org/W2138282914","https://openalex.org/W2065850627","https://openalex.org/W2017012638","https://openalex.org/W2071885361","https://openalex.org/W1966793535","https://openalex.org/W1964447062","https://openalex.org/W2088265144","https://openalex.org/W2386641302"],"abstract_inverted_index":{"The":[0,61,72],"process":[1],"of":[2],"mixed-signal":[3],"design":[4],"by":[5],"obtaining":[6],"characteristics":[7],"from":[8],"both":[9],"digital":[10],"and":[11,29,87],"analog":[12],"sphere":[13],"is":[14,41,53,64],"called":[15],"Real":[16],"Number":[17],"Modeling":[18],"(RNM).":[19],"In":[20,95],"RNM,":[21],"signals":[22],"can":[23],"be":[24],"represented":[25],"as":[26],"real-number":[27],"variables":[28],"change":[30],"their":[31],"values":[32],"at":[33],"each":[34],"discrete":[35],"event,":[36],"which":[37],"means":[38],"that":[39],"time":[40],"distinct.":[42],"A":[43],"SystemVerilog-based":[44],"real":[45],"number":[46],"model":[47,63,101],"for":[48],"a":[49,67],"Voltage-Controlled":[50],"Oscillator":[51],"(VCO)":[52],"proposed,":[54],"in":[55,77,105],"order":[56],"to":[57,66],"enhance":[58],"simulation":[59,73,106],"performance.":[60],"presented":[62],"compared":[65],"Verilog-AMS":[68,85],"based":[69],"VCO":[70],"model.":[71],"runs":[74],"took":[75],"place":[76],"Cadence":[78,88],"Virtuoso":[79],"-":[80],"AMS":[81],"Simulator":[82],"(for":[83,90],"the":[84,91,98],"model)":[86],"SimVision":[89],"proposed":[92,99],"SystemVerilog":[93,100],"model).":[94],"all":[96],"cases,":[97],"demonstrates":[102],"high":[103],"gains":[104],"run":[107],"time,":[108],"along":[109],"with":[110],"acceptable":[111],"accuracy.":[112]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1}],"updated_date":"2026-04-21T08:09:41.155169","created_date":"2025-10-10T00:00:00"}
