{"id":"https://openalex.org/W4256725767","doi":"https://doi.org/10.1109/mocast.2018.8376631","title":"Design of CPLD-based mealy FSMs with counters","display_name":"Design of CPLD-based mealy FSMs with counters","publication_year":2018,"publication_date":"2018-05-01","ids":{"openalex":"https://openalex.org/W4256725767","doi":"https://doi.org/10.1109/mocast.2018.8376631"},"language":"en","primary_location":{"id":"doi:10.1109/mocast.2018.8376631","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mocast.2018.8376631","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 7th International Conference on Modern Circuits and Systems Technologies (MOCAST)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5114017949","display_name":"Alexander Barkalov","orcid":null},"institutions":[{"id":"https://openalex.org/I46305939","display_name":"University of Zielona G\u00f3ra","ror":"https://ror.org/04fzm7v55","country_code":"PL","type":"education","lineage":["https://openalex.org/I46305939"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"Alexander Barkalov","raw_affiliation_strings":["Electronics and Computer Science Faculty of Computer, University of Zielona Gora Zielona G\u00f3ra, Poland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electronics and Computer Science Faculty of Computer, University of Zielona Gora Zielona G\u00f3ra, Poland","institution_ids":["https://openalex.org/I46305939"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5079123162","display_name":"Larysa Titarenko","orcid":"https://orcid.org/0000-0001-9558-3322"},"institutions":[{"id":"https://openalex.org/I46305939","display_name":"University of Zielona G\u00f3ra","ror":"https://ror.org/04fzm7v55","country_code":"PL","type":"education","lineage":["https://openalex.org/I46305939"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"Larysa Titarenko","raw_affiliation_strings":["Electronics and Computer Science Faculty of Computer, University of Zielona Gora Zielona G\u00f3ra, Poland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electronics and Computer Science Faculty of Computer, University of Zielona Gora Zielona G\u00f3ra, Poland","institution_ids":["https://openalex.org/I46305939"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5085989076","display_name":"S\u0142awomir Chmielewski","orcid":"https://orcid.org/0000-0001-9671-2800"},"institutions":[{"id":"https://openalex.org/I4210140734","display_name":"State Higher Vocational School in G\u0142og\u00f3w","ror":"https://ror.org/04wthrp69","country_code":"PL","type":"education","lineage":["https://openalex.org/I4210140734"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"Slawomir Chmielewski","raw_affiliation_strings":["Institute of Science and Technology, State University of Applied Sciences in Glogow, Glogow, Poland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Science and Technology, State University of Applied Sciences in Glogow, Glogow, Poland","institution_ids":["https://openalex.org/I4210140734"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.2619,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.61389897,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"53","issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T13292","display_name":"Embedded Systems and FPGA Applications","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T13292","display_name":"Embedded Systems and FPGA Applications","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/complex-programmable-logic-device","display_name":"Complex programmable logic device","score":0.9267064332962036},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7355808019638062},{"id":"https://openalex.org/keywords/state","display_name":"State (computer science)","score":0.535156786441803},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.507824718952179},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4576115012168884},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.4453990161418915},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.4397073984146118},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.43940597772598267},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4356077313423157},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.3985390365123749},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.18992558121681213},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1103413999080658}],"concepts":[{"id":"https://openalex.org/C128315158","wikidata":"https://www.wikidata.org/wiki/Q1063858","display_name":"Complex programmable logic device","level":2,"score":0.9267064332962036},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7355808019638062},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.535156786441803},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.507824718952179},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4576115012168884},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.4453990161418915},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.4397073984146118},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.43940597772598267},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4356077313423157},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3985390365123749},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.18992558121681213},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1103413999080658},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mocast.2018.8376631","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mocast.2018.8376631","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 7th International Conference on Modern Circuits and Systems Technologies (MOCAST)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.550000011920929,"display_name":"Zero hunger","id":"https://metadata.un.org/sdg/2"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W251131796","https://openalex.org/W598520007","https://openalex.org/W626514594","https://openalex.org/W1976773275","https://openalex.org/W2150864685","https://openalex.org/W2483541570","https://openalex.org/W2641437438","https://openalex.org/W4213095369","https://openalex.org/W4230904455"],"related_works":["https://openalex.org/W2348845661","https://openalex.org/W2047993371","https://openalex.org/W2381638859","https://openalex.org/W2114650875","https://openalex.org/W2197466303","https://openalex.org/W2374093018","https://openalex.org/W1984298705","https://openalex.org/W2117255572","https://openalex.org/W2007450186","https://openalex.org/W2462231960"],"abstract_inverted_index":{"A":[0],"method":[1,14],"is":[2,15,40],"proposed":[3,46],"for":[4],"hardware":[5],"reduction":[6],"of":[7,19,27,43,45],"CPLD-based":[8],"Mealy":[9],"FMS's":[10],"logic":[11],"circuit.":[12],"The":[13,25],"based":[16],"on":[17],"replacement":[18],"state":[20,23],"register":[21],"by":[22],"counter.":[24],"content":[26],"the":[28],"counter":[29],"can":[30],"be":[31],"increased":[32],"during":[33],"both":[34],"conditional":[35],"and":[36],"unconditional":[37],"transitions.":[38],"There":[39],"an":[41],"example":[42],"application":[44],"method.":[47]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
