{"id":"https://openalex.org/W2807949989","doi":"https://doi.org/10.1109/mocast.2018.8376568","title":"A very compact population count circuit for associative memories","display_name":"A very compact population count circuit for associative memories","publication_year":2018,"publication_date":"2018-05-01","ids":{"openalex":"https://openalex.org/W2807949989","doi":"https://doi.org/10.1109/mocast.2018.8376568","mag":"2807949989"},"language":"en","primary_location":{"id":"doi:10.1109/mocast.2018.8376568","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mocast.2018.8376568","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 7th International Conference on Modern Circuits and Systems Technologies (MOCAST)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5033404614","display_name":"L. Frontini","orcid":"https://orcid.org/0000-0002-1137-8629"},"institutions":[{"id":"https://openalex.org/I189158943","display_name":"University of Milan","ror":"https://ror.org/00wjc7c48","country_code":"IT","type":"education","lineage":["https://openalex.org/I189158943"]},{"id":"https://openalex.org/I4210136779","display_name":"Istituto Nazionale di Fisica Nucleare, Sezione di Milano","ror":"https://ror.org/04w4m6z96","country_code":"IT","type":"facility","lineage":["https://openalex.org/I160013858","https://openalex.org/I4210136779"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Luca Frontini","raw_affiliation_strings":["INFN, Universit\u00e0 degli Studi di Milano, Milano"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"INFN, Universit\u00e0 degli Studi di Milano, Milano","institution_ids":["https://openalex.org/I189158943","https://openalex.org/I4210136779"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5104437581","display_name":"Valentino Liberali","orcid":"https://orcid.org/0000-0003-1333-6876"},"institutions":[{"id":"https://openalex.org/I189158943","display_name":"University of Milan","ror":"https://ror.org/00wjc7c48","country_code":"IT","type":"education","lineage":["https://openalex.org/I189158943"]},{"id":"https://openalex.org/I4210136779","display_name":"Istituto Nazionale di Fisica Nucleare, Sezione di Milano","ror":"https://ror.org/04w4m6z96","country_code":"IT","type":"facility","lineage":["https://openalex.org/I160013858","https://openalex.org/I4210136779"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Valentino Liberali","raw_affiliation_strings":["INFN, Universit\u00e0 degli Studi di Milano, Milano"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"INFN, Universit\u00e0 degli Studi di Milano, Milano","institution_ids":["https://openalex.org/I189158943","https://openalex.org/I4210136779"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5041389564","display_name":"A. Stabile","orcid":"https://orcid.org/0000-0002-6868-8329"},"institutions":[{"id":"https://openalex.org/I189158943","display_name":"University of Milan","ror":"https://ror.org/00wjc7c48","country_code":"IT","type":"education","lineage":["https://openalex.org/I189158943"]},{"id":"https://openalex.org/I4210136779","display_name":"Istituto Nazionale di Fisica Nucleare, Sezione di Milano","ror":"https://ror.org/04w4m6z96","country_code":"IT","type":"facility","lineage":["https://openalex.org/I160013858","https://openalex.org/I4210136779"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Alberto Stabile","raw_affiliation_strings":["INFN, Universit\u00e0 degli Studi di Milano, Milano"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"INFN, Universit\u00e0 degli Studi di Milano, Milano","institution_ids":["https://openalex.org/I189158943","https://openalex.org/I4210136779"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3896,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.4596513,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"3"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9854999780654907,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9854999780654907,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11478","display_name":"Caching and Content Delivery","score":0.9641000032424927,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.9581000208854675,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7742159962654114},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.641655445098877},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5801610946655273},{"id":"https://openalex.org/keywords/associative-property","display_name":"Associative property","score":0.5659862160682678},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5591424107551575},{"id":"https://openalex.org/keywords/population","display_name":"Population","score":0.5116079449653625},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.45001405477523804},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.42602866888046265},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.40623384714126587},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.39271068572998047},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3313705325126648},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.30408570170402527},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.24983596801757812},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23825615644454956},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2061173915863037}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7742159962654114},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.641655445098877},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5801610946655273},{"id":"https://openalex.org/C159423971","wikidata":"https://www.wikidata.org/wiki/Q177251","display_name":"Associative property","level":2,"score":0.5659862160682678},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5591424107551575},{"id":"https://openalex.org/C2908647359","wikidata":"https://www.wikidata.org/wiki/Q2625603","display_name":"Population","level":2,"score":0.5116079449653625},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.45001405477523804},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.42602866888046265},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.40623384714126587},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.39271068572998047},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3313705325126648},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.30408570170402527},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.24983596801757812},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23825615644454956},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2061173915863037},{"id":"https://openalex.org/C144024400","wikidata":"https://www.wikidata.org/wiki/Q21201","display_name":"Sociology","level":0,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C202444582","wikidata":"https://www.wikidata.org/wiki/Q837863","display_name":"Pure mathematics","level":1,"score":0.0},{"id":"https://openalex.org/C149923435","wikidata":"https://www.wikidata.org/wiki/Q37732","display_name":"Demography","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mocast.2018.8376568","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mocast.2018.8376568","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2018 7th International Conference on Modern Circuits and Systems Technologies (MOCAST)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.5899999737739563}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1487917284","https://openalex.org/W2096646140","https://openalex.org/W2098406858","https://openalex.org/W2142345945","https://openalex.org/W2605423379","https://openalex.org/W2620933964","https://openalex.org/W2621141761","https://openalex.org/W4211046286","https://openalex.org/W6674220086"],"related_works":["https://openalex.org/W2072840391","https://openalex.org/W818963952","https://openalex.org/W2039140951","https://openalex.org/W2157277696","https://openalex.org/W2018106661","https://openalex.org/W2074526596","https://openalex.org/W1939541994","https://openalex.org/W4242010157","https://openalex.org/W1851795671","https://openalex.org/W2125277664"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,60,84],"new":[4],"population":[5],"count":[6],"circuit,":[7],"suitable":[8],"for":[9,19],"very":[10],"scaled":[11,37],"CMOS":[12,64],"technologies.":[13],"The":[14,53,75],"proposed":[15],"circuit":[16,42],"is":[17,43,79],"optimized":[18],"the":[20,25,41,50,67,70],"total":[21,76],"area,":[22],"instead":[23],"of":[24,27,35,69],"number":[26],"transistors,":[28],"in":[29,46,59],"order":[30,47],"to":[31,48,88],"take":[32],"full":[33],"advantage":[34],"deeply":[36],"technology":[38],"features.":[39],"Moreover,":[40],"purely":[44],"combinational,":[45],"simplify":[49],"control":[51],"logic.":[52],"envisaged":[54],"solution":[55],"has":[56,72],"been":[57,73],"designed":[58],"commercial":[61],"28":[62],"nm":[63],"technology,":[65],"and":[66],"design":[68],"layout":[71],"validated.":[74],"silicon":[77],"area":[78],"14.04":[80],"\u00d7":[81],"0.905":[82],"\u03bcm2for":[83],"counter":[85],"from":[86],"0":[87],"8.":[89]},"counts_by_year":[{"year":2019,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}