{"id":"https://openalex.org/W2621374815","doi":"https://doi.org/10.1109/mocast.2017.7937630","title":"Multi field SRAM access via intra-encoders and crossbar addressing scheme","display_name":"Multi field SRAM access via intra-encoders and crossbar addressing scheme","publication_year":2017,"publication_date":"2017-05-01","ids":{"openalex":"https://openalex.org/W2621374815","doi":"https://doi.org/10.1109/mocast.2017.7937630","mag":"2621374815"},"language":"en","primary_location":{"id":"doi:10.1109/mocast.2017.7937630","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mocast.2017.7937630","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5015547174","display_name":"\u0398\u03b5\u03cc\u03b4\u03c9\u03c1\u03bf\u03c2 \u03a3\u03b9\u03bc\u03cc\u03c0\u03bf\u03c5\u03bb\u03bf\u03c2","orcid":"https://orcid.org/0000-0002-2219-426X"},"institutions":[{"id":"https://openalex.org/I174878644","display_name":"University of Patras","ror":"https://ror.org/017wvtq80","country_code":"GR","type":"education","lineage":["https://openalex.org/I174878644"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Theodoros Simopoulos","raw_affiliation_strings":["Comp. Eng. & Informatics Dept., University of Patras, Rio, Patra, Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Comp. Eng. & Informatics Dept., University of Patras, Rio, Patra, Greece","institution_ids":["https://openalex.org/I174878644"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091288731","display_name":"Lazaros Spyridopoulos","orcid":null},"institutions":[{"id":"https://openalex.org/I21370196","display_name":"Aristotle University of Thessaloniki","ror":"https://ror.org/02j61yw88","country_code":"GR","type":"education","lineage":["https://openalex.org/I21370196"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Lazaros Spyridopoulos","raw_affiliation_strings":["Informatics Dept, Aristotle University of Thessaloniki, Thessaloniki, Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Informatics Dept, Aristotle University of Thessaloniki, Thessaloniki, Greece","institution_ids":["https://openalex.org/I21370196"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053637778","display_name":"George Alexiou","orcid":"https://orcid.org/0000-0003-2244-4916"},"institutions":[{"id":"https://openalex.org/I174878644","display_name":"University of Patras","ror":"https://ror.org/017wvtq80","country_code":"GR","type":"education","lineage":["https://openalex.org/I174878644"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"George Ph. Alexiou","raw_affiliation_strings":["Comp. Eng. & Informatics Dept., University of Patras, Rio, Patra, Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Comp. Eng. & Informatics Dept., University of Patras, Rio, Patra, Greece","institution_ids":["https://openalex.org/I174878644"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5087517264","display_name":"N. Konofaos","orcid":"https://orcid.org/0000-0003-2949-1184"},"institutions":[{"id":"https://openalex.org/I21370196","display_name":"Aristotle University of Thessaloniki","ror":"https://ror.org/02j61yw88","country_code":"GR","type":"education","lineage":["https://openalex.org/I21370196"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Nikos Konofaos","raw_affiliation_strings":["Informatics Dept, Aristotle University of Thessaloniki, Thessaloniki, Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Informatics Dept, Aristotle University of Thessaloniki, Thessaloniki, Greece","institution_ids":["https://openalex.org/I21370196"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.2312,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.4879088,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"1","issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/crossbar-switch","display_name":"Crossbar switch","score":0.8230395317077637},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7904186248779297},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6521193981170654},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6085917949676514},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.562757134437561},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.5511847138404846},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.5431796908378601},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.5302878022193909},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.48978614807128906},{"id":"https://openalex.org/keywords/field","display_name":"Field (mathematics)","score":0.4849541187286377},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.4758714735507965},{"id":"https://openalex.org/keywords/flat-memory-model","display_name":"Flat memory model","score":0.4754347801208496},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.4574339985847473},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.41911616921424866},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.38570746779441833}],"concepts":[{"id":"https://openalex.org/C29984679","wikidata":"https://www.wikidata.org/wiki/Q1929149","display_name":"Crossbar switch","level":2,"score":0.8230395317077637},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7904186248779297},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6521193981170654},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6085917949676514},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.562757134437561},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.5511847138404846},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.5431796908378601},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.5302878022193909},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.48978614807128906},{"id":"https://openalex.org/C9652623","wikidata":"https://www.wikidata.org/wiki/Q190109","display_name":"Field (mathematics)","level":2,"score":0.4849541187286377},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.4758714735507965},{"id":"https://openalex.org/C57863822","wikidata":"https://www.wikidata.org/wiki/Q905488","display_name":"Flat memory model","level":4,"score":0.4754347801208496},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.4574339985847473},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.41911616921424866},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.38570746779441833},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C202444582","wikidata":"https://www.wikidata.org/wiki/Q837863","display_name":"Pure mathematics","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mocast.2017.7937630","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mocast.2017.7937630","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W134990542","https://openalex.org/W1993475156","https://openalex.org/W2041633436","https://openalex.org/W2896376862","https://openalex.org/W3106111632","https://openalex.org/W6605533373"],"related_works":["https://openalex.org/W2044064773","https://openalex.org/W1575240748","https://openalex.org/W2047684617","https://openalex.org/W1837030695","https://openalex.org/W1975698617","https://openalex.org/W2162231486","https://openalex.org/W3025845664","https://openalex.org/W2049272650","https://openalex.org/W2168550483","https://openalex.org/W2766165550"],"abstract_inverted_index":{"In":[0],"this":[1],"work,":[2],"a":[3,14,46],"novel":[4],"architecture":[5],"that":[6],"simultaneously":[7],"accesses":[8],"multiple":[9],"and":[10,76],"non-overlapped":[11],"sub-regions":[12],"of":[13,23,40,49,62,79,107],"static":[15],"random":[16],"access":[17,106],"memory,":[18],"is":[19,28,43],"presented.":[20],"The":[21,38],"selection":[22],"the":[24,41,50,55,71,94,102,108],"multi":[25,104],"memory":[26,36,42,59,66,77,87],"fields":[27,78],"succeeded":[29],"via":[30],"intra-encoders,":[31],"placed":[32],"one":[33],"for":[34],"every":[35],"field.":[37],"addressing":[39,52],"done":[44],"using":[45,70],"modified":[47],"approach":[48],"crossbar":[51],"scheme.":[53],"At":[54,93],"presented":[56],"implementation,":[57],"each":[58],"field":[60,105],"comprises":[61],"8":[63,65],"by":[64],"cell":[67,88],"sectors.":[68],"However,":[69],"same":[72],"design":[73],"guidelines,":[74],"memories":[75],"bigger":[80],"size,":[81],"can":[82],"be":[83],"easily":[84],"created.":[85],"Each":[86],"uses":[89],"an":[90],"8T":[91],"model.":[92],"end,":[95],"simulation":[96],"results":[97],"are":[98],"presented,":[99],"which":[100],"verify":[101],"successful":[103],"memory.":[109]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
