{"id":"https://openalex.org/W2621072154","doi":"https://doi.org/10.1109/mocast.2017.7937623","title":"Designing Moore FSM with extended class codes","display_name":"Designing Moore FSM with extended class codes","publication_year":2017,"publication_date":"2017-05-01","ids":{"openalex":"https://openalex.org/W2621072154","doi":"https://doi.org/10.1109/mocast.2017.7937623","mag":"2621072154"},"language":"en","primary_location":{"id":"doi:10.1109/mocast.2017.7937623","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mocast.2017.7937623","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5043659905","display_name":"Kamil Mielcarek","orcid":"https://orcid.org/0000-0003-4027-7541"},"institutions":[{"id":"https://openalex.org/I46305939","display_name":"University of Zielona G\u00f3ra","ror":"https://ror.org/04fzm7v55","country_code":"PL","type":"education","lineage":["https://openalex.org/I46305939"]}],"countries":["PL"],"is_corresponding":true,"raw_author_name":"Kamil Mielcarek","raw_affiliation_strings":["Electronics and Computer Science, University of Zielona G\u00f3ra, Zielona G\u00f3ra, Poland"],"affiliations":[{"raw_affiliation_string":"Electronics and Computer Science, University of Zielona G\u00f3ra, Zielona G\u00f3ra, Poland","institution_ids":["https://openalex.org/I46305939"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5114017949","display_name":"Alexander Barkalov","orcid":null},"institutions":[{"id":"https://openalex.org/I46305939","display_name":"University of Zielona G\u00f3ra","ror":"https://ror.org/04fzm7v55","country_code":"PL","type":"education","lineage":["https://openalex.org/I46305939"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"Alexander Barkalov","raw_affiliation_strings":["Electronics and Computer Science, University of Zielona G\u00f3ra, Zielona G\u00f3ra, Poland"],"affiliations":[{"raw_affiliation_string":"Electronics and Computer Science, University of Zielona G\u00f3ra, Zielona G\u00f3ra, Poland","institution_ids":["https://openalex.org/I46305939"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5079123162","display_name":"Larysa Titarenko","orcid":"https://orcid.org/0000-0001-9558-3322"},"institutions":[{"id":"https://openalex.org/I46305939","display_name":"University of Zielona G\u00f3ra","ror":"https://ror.org/04fzm7v55","country_code":"PL","type":"education","lineage":["https://openalex.org/I46305939"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"Larysa Titarenko","raw_affiliation_strings":["Electronics and Computer Science, University of Zielona G\u00f3ra, Zielona G\u00f3ra, Poland"],"affiliations":[{"raw_affiliation_string":"Electronics and Computer Science, University of Zielona G\u00f3ra, Zielona G\u00f3ra, Poland","institution_ids":["https://openalex.org/I46305939"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5043659905"],"corresponding_institution_ids":["https://openalex.org/I46305939"],"apc_list":null,"apc_paid":null,"fwci":0.2253,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.47255626,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"38","issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7242444753646851},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.6284292340278625},{"id":"https://openalex.org/keywords/class","display_name":"Class (philosophy)","score":0.6027982234954834},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.5877406597137451},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4841173589229584},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.47119829058647156},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.4688979685306549},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.46148887276649475},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.44657790660858154},{"id":"https://openalex.org/keywords/automaton","display_name":"Automaton","score":0.43799158930778503},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.42082738876342773},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.37641939520835876},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3466966152191162},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.2832745909690857},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.12599945068359375},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11678043007850647},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.09264710545539856}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7242444753646851},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.6284292340278625},{"id":"https://openalex.org/C2777212361","wikidata":"https://www.wikidata.org/wiki/Q5127848","display_name":"Class (philosophy)","level":2,"score":0.6027982234954834},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.5877406597137451},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4841173589229584},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.47119829058647156},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.4688979685306549},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.46148887276649475},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.44657790660858154},{"id":"https://openalex.org/C112505250","wikidata":"https://www.wikidata.org/wiki/Q787116","display_name":"Automaton","level":2,"score":0.43799158930778503},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.42082738876342773},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.37641939520835876},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3466966152191162},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.2832745909690857},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.12599945068359375},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11678043007850647},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.09264710545539856}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mocast.2017.7937623","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mocast.2017.7937623","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W251131796","https://openalex.org/W1511688816","https://openalex.org/W2004846004","https://openalex.org/W2021809750","https://openalex.org/W2025851490","https://openalex.org/W2100404782","https://openalex.org/W2129183345","https://openalex.org/W2428599141","https://openalex.org/W2436959763","https://openalex.org/W4213095369","https://openalex.org/W4239427185"],"related_works":["https://openalex.org/W2155289750","https://openalex.org/W2159724425","https://openalex.org/W4231267350","https://openalex.org/W2117956479","https://openalex.org/W2086821903","https://openalex.org/W2053477566","https://openalex.org/W4255564979","https://openalex.org/W2746929098","https://openalex.org/W2059422871","https://openalex.org/W1966764473"],"abstract_inverted_index":{"A":[0],"method":[1,10,33],"is":[2,11],"proposed":[3],"for":[4],"designing":[5],"LUT-based":[6],"Moore":[7],"FSMs.":[8],"The":[9,32],"based":[12],"on":[13],"splitting":[14],"the":[15],"set":[16],"of":[17,19,26,30,42],"classes":[18],"pseudoequivalent":[20],"states.":[21],"There":[22],"are":[23],"given":[24],"example":[25],"design":[27],"and":[28],"results":[29],"investigations.":[31],"allows":[34],"obtaining":[35],"FSM":[36],"logic":[37],"circuits":[38],"having":[39],"less":[40],"amount":[41],"LUTs":[43],"than":[44],"known":[45],"from":[46],"literature":[47],"methods.":[48]},"counts_by_year":[{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}