{"id":"https://openalex.org/W2620894671","doi":"https://doi.org/10.1109/mocast.2017.7937618","title":"Design of LVDS driver and receiver in 28 nm CMOS technology for Associative Memories","display_name":"Design of LVDS driver and receiver in 28 nm CMOS technology for Associative Memories","publication_year":2017,"publication_date":"2017-05-01","ids":{"openalex":"https://openalex.org/W2620894671","doi":"https://doi.org/10.1109/mocast.2017.7937618","mag":"2620894671"},"language":"en","primary_location":{"id":"doi:10.1109/mocast.2017.7937618","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mocast.2017.7937618","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5061821503","display_name":"G. Traversi","orcid":"https://orcid.org/0000-0003-3977-6976"},"institutions":[{"id":"https://openalex.org/I11039511","display_name":"University of Bergamo","ror":"https://ror.org/02mbd5571","country_code":"IT","type":"education","lineage":["https://openalex.org/I11039511"]},{"id":"https://openalex.org/I4210109533","display_name":"Istituto Nazionale di Fisica Nucleare, Sezione di Pavia","ror":"https://ror.org/01st30669","country_code":"IT","type":"facility","lineage":["https://openalex.org/I160013858","https://openalex.org/I4210109533"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Gianluca Traversi","raw_affiliation_strings":["INFN Pavia, Italy","Universit\u00e0 degli Studi di Bergamo, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"INFN Pavia, Italy","institution_ids":["https://openalex.org/I4210109533"]},{"raw_affiliation_string":"Universit\u00e0 degli Studi di Bergamo, Italy","institution_ids":["https://openalex.org/I11039511"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070940935","display_name":"F. De Canio","orcid":"https://orcid.org/0000-0002-3303-3795"},"institutions":[{"id":"https://openalex.org/I4210109533","display_name":"Istituto Nazionale di Fisica Nucleare, Sezione di Pavia","ror":"https://ror.org/01st30669","country_code":"IT","type":"facility","lineage":["https://openalex.org/I160013858","https://openalex.org/I4210109533"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Francesco De Canio","raw_affiliation_strings":["INFN Pavia, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"INFN Pavia, Italy","institution_ids":["https://openalex.org/I4210109533"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5104437581","display_name":"Valentino Liberali","orcid":"https://orcid.org/0000-0003-1333-6876"},"institutions":[{"id":"https://openalex.org/I189158943","display_name":"University of Milan","ror":"https://ror.org/00wjc7c48","country_code":"IT","type":"education","lineage":["https://openalex.org/I189158943"]},{"id":"https://openalex.org/I4210136779","display_name":"Istituto Nazionale di Fisica Nucleare, Sezione di Milano","ror":"https://ror.org/04w4m6z96","country_code":"IT","type":"facility","lineage":["https://openalex.org/I160013858","https://openalex.org/I4210136779"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Valentino Liberali","raw_affiliation_strings":["INFN Milano, Italy","Universit\u00e0 degli Studi di Milano, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"INFN Milano, Italy","institution_ids":["https://openalex.org/I4210136779"]},{"raw_affiliation_string":"Universit\u00e0 degli Studi di Milano, Italy","institution_ids":["https://openalex.org/I189158943"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5041389564","display_name":"A. Stabile","orcid":"https://orcid.org/0000-0002-6868-8329"},"institutions":[{"id":"https://openalex.org/I4210136779","display_name":"Istituto Nazionale di Fisica Nucleare, Sezione di Milano","ror":"https://ror.org/04w4m6z96","country_code":"IT","type":"facility","lineage":["https://openalex.org/I160013858","https://openalex.org/I4210136779"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Alberto Stabile","raw_affiliation_strings":["INFN Milano, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"INFN Milano, Italy","institution_ids":["https://openalex.org/I4210136779"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.563,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.68294512,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":"26","issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9902999997138977,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9901999831199646,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.8064355254173279},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6909055709838867},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.679775595664978},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.5731096267700195},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.5527132153511047},{"id":"https://openalex.org/keywords/content-addressable-memory","display_name":"Content-addressable memory","score":0.5349852442741394},{"id":"https://openalex.org/keywords/associative-property","display_name":"Associative property","score":0.5187390446662903},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.4633181095123291},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4237833321094513},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4098513126373291},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.40098071098327637},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.34967780113220215},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3276924788951874},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.28004997968673706},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2572740316390991},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22017210721969604},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.20837834477424622},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.10762059688568115},{"id":"https://openalex.org/keywords/artificial-neural-network","display_name":"Artificial neural network","score":0.08277598023414612},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.0726499855518341}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.8064355254173279},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6909055709838867},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.679775595664978},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.5731096267700195},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.5527132153511047},{"id":"https://openalex.org/C53442348","wikidata":"https://www.wikidata.org/wiki/Q745101","display_name":"Content-addressable memory","level":3,"score":0.5349852442741394},{"id":"https://openalex.org/C159423971","wikidata":"https://www.wikidata.org/wiki/Q177251","display_name":"Associative property","level":2,"score":0.5187390446662903},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.4633181095123291},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4237833321094513},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4098513126373291},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.40098071098327637},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.34967780113220215},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3276924788951874},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.28004997968673706},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2572740316390991},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22017210721969604},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.20837834477424622},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.10762059688568115},{"id":"https://openalex.org/C50644808","wikidata":"https://www.wikidata.org/wiki/Q192776","display_name":"Artificial neural network","level":2,"score":0.08277598023414612},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0726499855518341},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C202444582","wikidata":"https://www.wikidata.org/wiki/Q837863","display_name":"Pure mathematics","level":1,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/mocast.2017.7937618","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mocast.2017.7937618","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST)","raw_type":"proceedings-article"},{"id":"pmh:oai:aisberg.unibg.it:10446/112984","is_oa":false,"landing_page_url":"http://hdl.handle.net/10446/112984","pdf_url":null,"source":{"id":"https://openalex.org/S4377196347","display_name":"Aisberg (University of Bergamo)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I11039511","host_organization_name":"University of Bergamo","host_organization_lineage":["https://openalex.org/I11039511"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8899999856948853,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1499572629","https://openalex.org/W1551927311","https://openalex.org/W2056003518","https://openalex.org/W2108034570","https://openalex.org/W2149790314","https://openalex.org/W2419054949","https://openalex.org/W4300993850"],"related_works":["https://openalex.org/W3014521742","https://openalex.org/W2617868873","https://openalex.org/W3204141294","https://openalex.org/W4386230336","https://openalex.org/W4306968100","https://openalex.org/W1492794944","https://openalex.org/W279701215","https://openalex.org/W2107697999","https://openalex.org/W1902246517","https://openalex.org/W3145837419"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"the":[3,12,38,64,70],"design":[4,78],"of":[5,15,22,40,58,69],"a":[6,26,55,92],"LVDS":[7],"input/output":[8],"interface":[9],"circuit":[10],"for":[11,86],"next":[13],"generation":[14],"Associative":[16,23],"Memory":[17],"(AM)":[18],"chip.":[19],"The":[20,77],"bandwidth":[21],"Memories":[24],"is":[25,46],"critical":[27],"aspect":[28],"that":[29],"needs":[30],"to":[31,36,47],"be":[32,61],"addressed":[33],"in":[34,63,80,88,91],"order":[35],"increase":[37],"number":[39,57],"comparisons":[41],"per":[42],"second.":[43],"Our":[44],"aim":[45],"transfer":[48],"parallel":[49],"buses":[50],"at":[51],"500":[52],"MHz.":[53],"Since":[54],"large":[56],"receivers/drivers":[59],"will":[60],"included":[62],"AM":[65],"chip,":[66],"power":[67],"consumption":[68],"circuits":[71],"has":[72,83],"been":[73,84],"taken":[74],"into":[75],"account.":[76],"discussed":[79],"this":[81],"work":[82],"submitted":[85],"fabrication":[87],"December":[89],"2016":[90],"28":[93],"nm":[94],"CMOS":[95],"technology.":[96]},"counts_by_year":[{"year":2023,"cited_by_count":2},{"year":2021,"cited_by_count":3},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":1}],"updated_date":"2026-07-02T09:51:11.867554","created_date":"2025-10-10T00:00:00"}
