{"id":"https://openalex.org/W2139600345","doi":"https://doi.org/10.1109/mmse.2002.1181631","title":"The impact of SMT/SMP designs on multimedia software engineering - a workload analysis study","display_name":"The impact of SMT/SMP designs on multimedia software engineering - a workload analysis study","publication_year":2003,"publication_date":"2003-06-26","ids":{"openalex":"https://openalex.org/W2139600345","doi":"https://doi.org/10.1109/mmse.2002.1181631","mag":"2139600345"},"language":"en","primary_location":{"id":"doi:10.1109/mmse.2002.1181631","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mmse.2002.1181631","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Fourth International Symposium on Multimedia Software Engineering, 2002. Proceedings.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5042651234","display_name":"Yen-Kuang Chen","orcid":"https://orcid.org/0000-0003-4546-9497"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB","US"],"is_corresponding":true,"raw_author_name":"Yen-Kuang Chen","raw_affiliation_strings":["Microprocessor Research Laboratories, Intel Corporation, USA","Intel Corporation"],"affiliations":[{"raw_affiliation_string":"Microprocessor Research Laboratories, Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5009744749","display_name":"Rainer Lienhart","orcid":"https://orcid.org/0000-0003-4007-6889"},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]},{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["GB","US"],"is_corresponding":false,"raw_author_name":"R. Lienhart","raw_affiliation_strings":["Microprocessor Research Laboratories, Intel Corporation, USA","Intel Corporation"],"affiliations":[{"raw_affiliation_string":"Microprocessor Research Laboratories, Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023964704","display_name":"Eric Debes","orcid":null},"institutions":[{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]},{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["GB","US"],"is_corresponding":false,"raw_author_name":"E. Debes","raw_affiliation_strings":["Microprocessor Research Laboratories, Intel Corporation, USA","Intel Corporation"],"affiliations":[{"raw_affiliation_string":"Microprocessor Research Laboratories, Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057389931","display_name":"Matthew J. Holliman","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB","US"],"is_corresponding":false,"raw_author_name":"M. Holliman","raw_affiliation_strings":["Microprocessor Research Laboratories, Intel Corporation, USA","Intel Corporation"],"affiliations":[{"raw_affiliation_string":"Microprocessor Research Laboratories, Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109230909","display_name":"M. Yeung","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB","US"],"is_corresponding":false,"raw_author_name":"M. Yeung","raw_affiliation_strings":["Microprocessor Research Laboratories, Intel Corporation, USA","Intel Corporation"],"affiliations":[{"raw_affiliation_string":"Microprocessor Research Laboratories, Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5042651234"],"corresponding_institution_ids":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"],"apc_list":null,"apc_paid":null,"fwci":1.2577,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.81188505,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"336","last_page":"343"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12720","display_name":"Multimedia Communication and Technology","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/3312","display_name":"Sociology and Political Science"},"field":{"id":"https://openalex.org/fields/33","display_name":"Social Sciences"},"domain":{"id":"https://openalex.org/domains/2","display_name":"Social Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8937326073646545},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.7372756600379944},{"id":"https://openalex.org/keywords/instruction-prefetch","display_name":"Instruction prefetch","score":0.606837272644043},{"id":"https://openalex.org/keywords/multithreading","display_name":"Multithreading","score":0.5706047415733337},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.5274080634117126},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.49497121572494507},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.4875592589378357},{"id":"https://openalex.org/keywords/locality","display_name":"Locality","score":0.45466840267181396},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4455394446849823},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.44336527585983276},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.4130095839500427},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.4107925295829773},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.40251779556274414},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3492426872253418},{"id":"https://openalex.org/keywords/thread","display_name":"Thread (computing)","score":0.16690096259117126}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8937326073646545},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.7372756600379944},{"id":"https://openalex.org/C133588205","wikidata":"https://www.wikidata.org/wiki/Q28455645","display_name":"Instruction prefetch","level":3,"score":0.606837272644043},{"id":"https://openalex.org/C201410400","wikidata":"https://www.wikidata.org/wiki/Q1064412","display_name":"Multithreading","level":3,"score":0.5706047415733337},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.5274080634117126},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.49497121572494507},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.4875592589378357},{"id":"https://openalex.org/C2779808786","wikidata":"https://www.wikidata.org/wiki/Q6664603","display_name":"Locality","level":2,"score":0.45466840267181396},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4455394446849823},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.44336527585983276},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.4130095839500427},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.4107925295829773},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.40251779556274414},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3492426872253418},{"id":"https://openalex.org/C138101251","wikidata":"https://www.wikidata.org/wiki/Q213092","display_name":"Thread (computing)","level":2,"score":0.16690096259117126},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mmse.2002.1181631","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mmse.2002.1181631","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Fourth International Symposium on Multimedia Software Engineering, 2002. Proceedings.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W63944998","https://openalex.org/W2105560386","https://openalex.org/W2112076978","https://openalex.org/W2139212933","https://openalex.org/W2252168276","https://openalex.org/W6602613798","https://openalex.org/W6676769703"],"related_works":["https://openalex.org/W2462146500","https://openalex.org/W2086718556","https://openalex.org/W2167303720","https://openalex.org/W2012518269","https://openalex.org/W2163134761","https://openalex.org/W2046128376","https://openalex.org/W2363672756","https://openalex.org/W2109715593","https://openalex.org/W57688818","https://openalex.org/W1496086148"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"the":[3,67,70,78,94,102],"study":[4],"of":[5],"running":[6],"several":[7],"core":[8],"multimedia":[9,22,26],"applications":[10],"on":[11,50],"a":[12,118],"simultaneous":[13],"multithreading":[14],"(SMT)":[15],"architecture":[16],"and":[17,45,59,65,88,100],"derives":[18],"design":[19],"principles":[20],"for":[21,107,128],"software":[23],"engineering.":[24],"The":[25,73],"workloads":[27],"range":[28],"from":[29],"memory":[30],"to":[31,37,47,120,133],"computational-bounded":[32],"kernels.":[33],"A":[34],"performance":[35,41,91],"metric":[36],"evaluate":[38],"effective":[39],"SMT":[40,61,81],"gain":[42],"is":[43],"introduced,":[44],"compared":[46],"similar":[48],"metrics":[49],"symmetric":[51],"multiprocessor":[52],"(SMP)":[53],"systems.":[54],"In":[55],"addition,":[56],"we":[57],"analyze":[58],"compare":[60],"versus":[62],"SMP":[63],"systems,":[64],"highlight":[66],"advantages":[68],"in":[69,80,131],"studied":[71],"applications.":[72],"results":[74],"indicate":[75],"that":[76,124],"sharing":[77,93],"cache":[79,86,95,98,104,135],"processors":[82],"can":[83,96],"provide":[84],"better":[85,90],"locality":[87],"thus":[89],"although":[92],"introduce":[97],"conflicts":[99],"reduce":[101,134],"actual":[103],"size":[105],"available":[106],"each":[108,129],"logical":[109],"processor.":[110],"We":[111],"also":[112],"propose":[113],"\"mutually":[114],"beneficial":[115],"prefetching\"":[116],"-":[117],"technique":[119],"schedule":[121],"threads":[122],"so":[123],"they":[125],"prefetch":[126],"data":[127],"other":[130],"order":[132],"miss":[136],"penalty.":[137]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
