{"id":"https://openalex.org/W4412939760","doi":"https://doi.org/10.1109/mm.2025.3594150","title":"BiFrost: A Composable, Resilient Interconnect Network Architecture for Scalable Artificial Intelligence Systems","display_name":"BiFrost: A Composable, Resilient Interconnect Network Architecture for Scalable Artificial Intelligence Systems","publication_year":2025,"publication_date":"2025-08-04","ids":{"openalex":"https://openalex.org/W4412939760","doi":"https://doi.org/10.1109/mm.2025.3594150"},"language":"en","primary_location":{"id":"doi:10.1109/mm.2025.3594150","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mm.2025.3594150","pdf_url":null,"source":{"id":"https://openalex.org/S59697426","display_name":"IEEE Micro","issn_l":"0272-1732","issn":["0272-1732","1937-4143"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Micro","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5072395015","display_name":"Gurpreet S. Kalsi","orcid":"https://orcid.org/0009-0000-7018-7585"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Gurpreet Singh Kalsi","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":"https://orcid.org/0009-0000-7018-7585","affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Hong Wang","orcid":"https://orcid.org/0009-0008-8204-6454"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210128612","display_name":"Mission College","ror":"https://ror.org/035fpgr29","country_code":"US","type":"education","lineage":["https://openalex.org/I4210128612"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hong Wang","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA","Intel Foundry, Santa Clara, CA, USA"],"raw_orcid":"https://orcid.org/0009-0008-8204-6454","affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Foundry, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700","https://openalex.org/I4210128612"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102833447","display_name":"Jason Howard","orcid":"https://orcid.org/0009-0005-6250-6108"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jason M. Howard","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":"https://orcid.org/0009-0005-6250-6108","affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066777272","display_name":"Joshua B Fryman","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Joshua B. Fryman","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066195314","display_name":"Fabrizio Petrini","orcid":"https://orcid.org/0000-0002-4977-7107"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Fabrizio Petrini","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA","Intel Labs, Santa Clara, CA, USA"],"raw_orcid":"https://orcid.org/0000-0002-4977-7107","affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Labs, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070391275","display_name":"D. Klowden","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Daniel S. Klowden","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5024682085","display_name":"Sanjaya Tayal","orcid":"https://orcid.org/0009-0006-3429-6534"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sanjaya Tayal","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006817639","display_name":"Anil V. Rao","orcid":"https://orcid.org/0000-0001-9038-7701"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Anil Rao","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5061946206","display_name":"Steve Pawlowski","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Steve Pawlowski","raw_affiliation_strings":["Intel Foundry, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Foundry, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":9,"corresponding_author_ids":["https://openalex.org/A5072395015"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":1.3517,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.84257382,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":96,"max":98},"biblio":{"volume":"45","issue":"5","first_page":"67","last_page":"78"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9965000152587891,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9965000152587891,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9768999814987183,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9761999845504761,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.9006080627441406},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.7021358609199524},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6505773663520813},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6494678854942322},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.6147629022598267},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.44295769929885864},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4169120788574219},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.304548442363739},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.25979888439178467}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.9006080627441406},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.7021358609199524},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6505773663520813},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6494678854942322},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.6147629022598267},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.44295769929885864},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4169120788574219},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.304548442363739},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.25979888439178467},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mm.2025.3594150","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mm.2025.3594150","pdf_url":null,"source":{"id":"https://openalex.org/S59697426","display_name":"IEEE Micro","issn_l":"0272-1732","issn":["0272-1732","1937-4143"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Micro","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2069623792","https://openalex.org/W2121758805","https://openalex.org/W2293821175","https://openalex.org/W4205608751","https://openalex.org/W4394966781"],"related_works":["https://openalex.org/W2014709025","https://openalex.org/W2155019192","https://openalex.org/W2389214306","https://openalex.org/W3125341812","https://openalex.org/W1991674760","https://openalex.org/W1668171714","https://openalex.org/W2965083567","https://openalex.org/W2155297398","https://openalex.org/W2889526943","https://openalex.org/W2038503502"],"abstract_inverted_index":{"Large":[0],"Language":[1],"Models":[2],"demand":[3],"extreme":[4],"memory":[5,17,97],"bandwidth":[6,61,139],"and":[7,15,27,53,62,95,120,133,144],"compute":[8,81],"density,":[9],"surpassing":[10],"traditional":[11],"architectures.":[12],"Chiplet-based":[13],"designs":[14],"3D":[16],"stacking":[18],"offer":[19],"solutions,":[20],"but":[21],"introduce":[22],"challenges":[23,40],"in":[24,66],"integration,":[25],"yield,":[26],"software":[28],"compatibility.":[29],"We":[30],"present":[31],"BiFrost,":[32],"a":[33,46,67,77,106],"composable":[34],"network":[35,48],"architecture":[36],"that":[37],"addresses":[38],"these":[39],"through":[41,92],"three":[42],"innovations.":[43],"BiFrost":[44,109,135],"implements":[45],"FatTree":[47],"on":[49,105],"chiplets,":[50],"enabling":[51,148],"intra-":[52],"inter-chiplet":[54],"communication":[55],"with":[56,85],"820":[57],"TB/s":[58],"aggregate":[59],"raw":[60],"sub-100":[63],"ns":[64],"latency":[65],"24":[68],"chiplet":[69,153],"setup.":[70],"A":[71],"unified":[72],"address":[73,80],"space,":[74],"enabled":[75],"by":[76],"novel":[78],"packet":[79],"unit,":[82],"ensures":[83],"compatibility":[84],"POSIX":[86],"shared-memory":[87],"models.":[88],"Resilience":[89],"is":[90],"achieved":[91],"adaptive":[93],"routing":[94,128],"dynamic":[96],"remapping,":[98],"ensuring":[99],"graceful":[100],"degradation":[101],"upon":[102],"faults.":[103],"Built":[104],"3nm":[107],"process,":[108],"features":[110],"0.48":[111],"mm<sup":[112,122],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[113,123],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[114,124],"per":[115,125],"16":[116,118],"\u00d7":[117],"router":[119],"17.2":[121],"chiplet.":[126],"Flexible":[127],"supports":[129],"topologies":[130],"like":[131],"Dragonfly":[132],"HyperX.":[134],"maintains":[136],"90%":[137],"peak":[138],"under":[140],"uniform":[141],"random":[142],"traffic":[143],"offers":[145],"OS-level":[146],"configurability,":[147],"seamless":[149],"scaling":[150],"from":[151],"single":[152],"to":[154],"multi-rack":[155],"systems.":[156]},"counts_by_year":[{"year":2026,"cited_by_count":1}],"updated_date":"2025-11-11T23:18:09.558992","created_date":"2025-10-10T00:00:00"}