{"id":"https://openalex.org/W4401328687","doi":"https://doi.org/10.1109/mm.2024.3436008","title":"A Comparison of Single-Ended, NRZ Unidirectional Signaling and Single-Ended, NRZ Simultaneous-Bidirectional Signaling for Die-to-Die Links","display_name":"A Comparison of Single-Ended, NRZ Unidirectional Signaling and Single-Ended, NRZ Simultaneous-Bidirectional Signaling for Die-to-Die Links","publication_year":2024,"publication_date":"2024-08-05","ids":{"openalex":"https://openalex.org/W4401328687","doi":"https://doi.org/10.1109/mm.2024.3436008"},"language":"en","primary_location":{"id":"doi:10.1109/mm.2024.3436008","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mm.2024.3436008","pdf_url":null,"source":{"id":"https://openalex.org/S59697426","display_name":"IEEE Micro","issn_l":"0272-1732","issn":["0272-1732","1937-4143"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Micro","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5067922746","display_name":"Durand Jarrett-Amor","orcid":"https://orcid.org/0000-0003-3162-3422"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Durand Jarrett-Amor","raw_affiliation_strings":["University of Toronto, Toronto, ON, Canada","University of Toronto, Toronto, ON, CA"],"raw_orcid":"https://orcid.org/0000-0003-3162-3422","affiliations":[{"raw_affiliation_string":"University of Toronto, Toronto, ON, Canada","institution_ids":["https://openalex.org/I185261750"]},{"raw_affiliation_string":"University of Toronto, Toronto, ON, CA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5010704016","display_name":"Anthony Chan Carusone","orcid":"https://orcid.org/0000-0002-0977-7516"},"institutions":[{"id":"https://openalex.org/I185261750","display_name":"University of Toronto","ror":"https://ror.org/03dbr7087","country_code":"CA","type":"education","lineage":["https://openalex.org/I185261750"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Tony Chan Carusone","raw_affiliation_strings":["University of Toronto, Toronto, ON, Canada","University of Toronto, Toronto, ON, CA"],"raw_orcid":"https://orcid.org/0000-0002-0977-7516","affiliations":[{"raw_affiliation_string":"University of Toronto, Toronto, ON, Canada","institution_ids":["https://openalex.org/I185261750"]},{"raw_affiliation_string":"University of Toronto, Toronto, ON, CA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5067922746"],"corresponding_institution_ids":["https://openalex.org/I185261750"],"apc_list":null,"apc_paid":null,"fwci":2.3718,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.89607965,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":96,"max":98},"biblio":{"volume":"45","issue":"1","first_page":"48","last_page":"56"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.6086000204086304,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.6086000204086304,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11741","display_name":"Flexible and Reconfigurable Manufacturing Systems","score":0.5228000283241272,"subfield":{"id":"https://openalex.org/subfields/2209","display_name":"Industrial and Manufacturing Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11932","display_name":"Wireless Body Area Networks","score":0.5088000297546387,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/die","display_name":"Die (integrated circuit)","score":0.9065848588943481},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6886945962905884},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.345283567905426},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12022566795349121}],"concepts":[{"id":"https://openalex.org/C111106434","wikidata":"https://www.wikidata.org/wiki/Q1072430","display_name":"Die (integrated circuit)","level":2,"score":0.9065848588943481},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6886945962905884},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.345283567905426},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12022566795349121},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mm.2024.3436008","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mm.2024.3436008","pdf_url":null,"source":{"id":"https://openalex.org/S59697426","display_name":"IEEE Micro","issn_l":"0272-1732","issn":["0272-1732","1937-4143"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Micro","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2742313288","https://openalex.org/W2929880560","https://openalex.org/W3016874508","https://openalex.org/W4252252652","https://openalex.org/W4392255268"],"related_works":["https://openalex.org/W4391375266","https://openalex.org/W2748952813","https://openalex.org/W2042913821","https://openalex.org/W2372289614","https://openalex.org/W2629813803","https://openalex.org/W2041067810","https://openalex.org/W2250518232","https://openalex.org/W3199170188","https://openalex.org/W2360137025","https://openalex.org/W2362738566"],"abstract_inverted_index":{"This":[0],"article":[1],"compares":[2],"single-ended,":[3,9],"NRZ":[4,10],"unidirectional":[5],"(UD)":[6],"signaling":[7,13,67],"to":[8,47],"simultaneous":[11,42],"bidirectional":[12,43],"for":[14,32,65,80],"ultrashort-reach":[15],"(USR)":[16],"die-to-die":[17],"(D2D)":[18],"links":[19,87],"in":[20,71,88],"terms":[21,72],"of":[22,73,84],"power":[23,50],"and":[24,39,52,77],"bit":[25],"error":[26],"rate":[27],"(BER).":[28],"We":[29],"show":[30],"that":[31],"the":[33,62,74],"same":[34],"transceiver":[35],"architecture,":[36],"aggregate":[37],"bandwidth,":[38],"BER,":[40],"a":[41,53,58],"link":[44],"is":[45,69],"able":[46],"achieve":[48],"better":[49],"efficiency":[51],"wider":[54],"eye":[55],"opening":[56],"than":[57],"UD":[59],"link.":[60],"Furthermore,":[61],"signal-integrity":[63],"constraints":[64],"each":[66],"approach":[68],"examined":[70],"insertion-loss-to-crosstalk":[75],"ratio":[76,79],"main-cursor-to-crosstalk":[78],"three":[81],"different":[82],"arrangements":[83],"USR":[85],"D2D":[86],"organic":[89],"substrates.":[90]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":4}],"updated_date":"2025-12-26T23:08:49.675405","created_date":"2024-08-06T00:00:00"}
