{"id":"https://openalex.org/W4388556637","doi":"https://doi.org/10.1109/mm.2023.3328832","title":"Pipelined and Partitionable Forward Error Correction and Cyclic Redundancy Check Circuitry Implementation for PCI Express 6.0 and Compute Express Link 3.0","display_name":"Pipelined and Partitionable Forward Error Correction and Cyclic Redundancy Check Circuitry Implementation for PCI Express 6.0 and Compute Express Link 3.0","publication_year":2023,"publication_date":"2023-11-10","ids":{"openalex":"https://openalex.org/W4388556637","doi":"https://doi.org/10.1109/mm.2023.3328832"},"language":"en","primary_location":{"id":"doi:10.1109/mm.2023.3328832","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mm.2023.3328832","pdf_url":null,"source":{"id":"https://openalex.org/S59697426","display_name":"IEEE Micro","issn_l":"0272-1732","issn":["0272-1732","1937-4143"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Micro","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5065609181","display_name":"Debendra Das Sharma","orcid":"https://orcid.org/0000-0003-1530-7788"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Debendra Das Sharma","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA"],"raw_orcid":"https://orcid.org/0000-0003-1530-7788","affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5008903675","display_name":"Swadesh Choudhary","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Swadesh Choudhary","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.569,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.69158798,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"44","issue":"2","first_page":"50","last_page":"59"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9955999851226807,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9945999979972839,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.6592890620231628},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6524944305419922},{"id":"https://openalex.org/keywords/conventional-pci","display_name":"Conventional PCI","score":0.5959007143974304},{"id":"https://openalex.org/keywords/link","display_name":"Link (geometry)","score":0.5879853963851929},{"id":"https://openalex.org/keywords/cyclic-redundancy-check","display_name":"Cyclic redundancy check","score":0.49398690462112427},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.46010008454322815},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.4583664536476135},{"id":"https://openalex.org/keywords/pci-express","display_name":"PCI Express","score":0.4567613899707794},{"id":"https://openalex.org/keywords/error-detection-and-correction","display_name":"Error detection and correction","score":0.4433749318122864},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.32862329483032227},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3046761155128479},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2501281499862671},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.24379974603652954},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.2430397868156433},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.17074444890022278},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.12011891603469849},{"id":"https://openalex.org/keywords/psychology","display_name":"Psychology","score":0.07621580362319946}],"concepts":[{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.6592890620231628},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6524944305419922},{"id":"https://openalex.org/C45393284","wikidata":"https://www.wikidata.org/wiki/Q191012","display_name":"Conventional PCI","level":3,"score":0.5959007143974304},{"id":"https://openalex.org/C2778753846","wikidata":"https://www.wikidata.org/wiki/Q6554239","display_name":"Link (geometry)","level":2,"score":0.5879853963851929},{"id":"https://openalex.org/C137627569","wikidata":"https://www.wikidata.org/wiki/Q245471","display_name":"Cyclic redundancy check","level":3,"score":0.49398690462112427},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.46010008454322815},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.4583664536476135},{"id":"https://openalex.org/C64270927","wikidata":"https://www.wikidata.org/wiki/Q206924","display_name":"PCI Express","level":3,"score":0.4567613899707794},{"id":"https://openalex.org/C103088060","wikidata":"https://www.wikidata.org/wiki/Q1062839","display_name":"Error detection and correction","level":2,"score":0.4433749318122864},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.32862329483032227},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3046761155128479},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2501281499862671},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.24379974603652954},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.2430397868156433},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.17074444890022278},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.12011891603469849},{"id":"https://openalex.org/C15744967","wikidata":"https://www.wikidata.org/wiki/Q9418","display_name":"Psychology","level":0,"score":0.07621580362319946},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.0},{"id":"https://openalex.org/C500558357","wikidata":"https://www.wikidata.org/wiki/Q12152","display_name":"Myocardial infarction","level":2,"score":0.0},{"id":"https://openalex.org/C118552586","wikidata":"https://www.wikidata.org/wiki/Q7867","display_name":"Psychiatry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mm.2023.3328832","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mm.2023.3328832","pdf_url":null,"source":{"id":"https://openalex.org/S59697426","display_name":"IEEE Micro","issn_l":"0272-1732","issn":["0272-1732","1937-4143"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Micro","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1534925464","https://openalex.org/W2108141042","https://openalex.org/W3107819383","https://openalex.org/W4205612694","https://openalex.org/W4387805935"],"related_works":["https://openalex.org/W1974765181","https://openalex.org/W2072972217","https://openalex.org/W2384704932","https://openalex.org/W2168697878","https://openalex.org/W2336971965","https://openalex.org/W2348004688","https://openalex.org/W3022412054","https://openalex.org/W16515434","https://openalex.org/W2036092231","https://openalex.org/W2387162708"],"abstract_inverted_index":{"The":[0],"sixth":[1],"generation":[2],"of":[3,68,134,149],"PCIe":[4,58,76],"(PCIe":[5],"6.0)":[6],"specification":[7],"adopted":[8],"four-level":[9],"pulse-amplitude":[10],"modulation":[11],"signaling":[12],"at":[13],"64":[14],"GT/s":[15],"for":[16,90,95,110,137],"maintaining":[17],"the":[18,71,93,104,138],"same":[19],"channel":[20],"reach,":[21],"cost,":[22],"and":[23,40,50,70,78,87,92,99,140],"power":[24],"profile":[25],"as":[26],"previous":[27],"generations.":[28],"Lightweight":[29],"forward":[30],"error":[31],"correction":[32],"(FEC),":[33],"a":[34,85,111,131,144],"strong":[35],"cyclic":[36],"redundancy":[37],"check":[38],"(CRC),":[39],"link-level":[41],"replay":[42],"mechanisms":[43],"deliver":[44],"low":[45],"latency,":[46],"high":[47,51],"bandwidth":[48],"efficiency,":[49],"reliability.":[52],"Compute":[53],"Express":[54],"Link":[55],"(CXL)":[56],"uses":[57],"6.0":[59,77],"physical":[60],"layer":[61],"with":[62,121,143],"latency-optimization":[63],"mechanisms.":[64],"Our":[65],"nonpipelined":[66],"implementation":[67,89],"FEC":[69,91,145],"CRC":[72,94,147],"is":[73],"incorporated":[74],"into":[75],"CXL":[79],"3.0":[80],"specifications.":[81],"We":[82],"also":[83],"propose":[84],"partitionable":[86,116,127],"pipelined":[88],"lowering":[96],"gate":[97,132],"count":[98,133],"latency.":[100],"Synthesis":[101],"results":[102],"from":[103],"Synopsys":[105],"Design":[106],"Compiler":[107],"demonstrates":[108],"that":[109],"16-lane":[112],"(x16)":[113],"PCIe/CXL":[114],"link":[115],"to":[117,119],"up":[118],"x4s,":[120],"four":[122],"independent":[123],"controllers":[124],"using":[125],"independently":[126],"logic,":[128],"we":[129],"achieve":[130],"approximately":[135],"100,000":[136],"transmit":[139],"receive":[141],"side":[142],"+":[146],"delay":[148],"less":[150],"than":[151],"1":[152],"ns":[153],"in":[154],"each":[155],"direction.":[156]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}