{"id":"https://openalex.org/W4324292875","doi":"https://doi.org/10.1109/mm.2023.3256796","title":"NVIDIA Hopper H100 GPU: Scaling Performance","display_name":"NVIDIA Hopper H100 GPU: Scaling Performance","publication_year":2023,"publication_date":"2023-03-14","ids":{"openalex":"https://openalex.org/W4324292875","doi":"https://doi.org/10.1109/mm.2023.3256796"},"language":"en","primary_location":{"id":"doi:10.1109/mm.2023.3256796","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mm.2023.3256796","pdf_url":null,"source":{"id":"https://openalex.org/S59697426","display_name":"IEEE Micro","issn_l":"0272-1732","issn":["0272-1732","1937-4143"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Micro","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5082568014","display_name":"Jack Choquette","orcid":"https://orcid.org/0000-0002-3282-6777"},"institutions":[{"id":"https://openalex.org/I4210127875","display_name":"Nvidia (United States)","ror":"https://ror.org/03jdj4y14","country_code":"US","type":"company","lineage":["https://openalex.org/I4210127875"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Jack Choquette","raw_affiliation_strings":["NVIDIA, Santa Clara, CA, USA"],"raw_orcid":"https://orcid.org/0000-0002-3282-6777","affiliations":[{"raw_affiliation_string":"NVIDIA, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I4210127875"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5082568014"],"corresponding_institution_ids":["https://openalex.org/I4210127875"],"apc_list":null,"apc_paid":null,"fwci":39.2008,"has_fulltext":false,"cited_by_count":131,"citation_normalized_percentile":{"value":0.99984761,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":98,"max":100},"biblio":{"volume":"43","issue":"3","first_page":"9","last_page":"17"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10715","display_name":"Distributed and Parallel Computing Systems","score":0.9839000105857849,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9815999865531921,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8737368583679199},{"id":"https://openalex.org/keywords/cuda","display_name":"CUDA","score":0.7502185106277466},{"id":"https://openalex.org/keywords/gpu-cluster","display_name":"GPU cluster","score":0.6004711985588074},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5695482492446899},{"id":"https://openalex.org/keywords/analytics","display_name":"Analytics","score":0.5434158444404602},{"id":"https://openalex.org/keywords/graphics-processing-unit","display_name":"Graphics processing unit","score":0.5307334065437317},{"id":"https://openalex.org/keywords/supercomputer","display_name":"Supercomputer","score":0.5134585499763489},{"id":"https://openalex.org/keywords/general-purpose-computing-on-graphics-processing-units","display_name":"General-purpose computing on graphics processing units","score":0.5129708647727966},{"id":"https://openalex.org/keywords/tensor","display_name":"Tensor (intrinsic definition)","score":0.5071218013763428},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.5033087134361267},{"id":"https://openalex.org/keywords/scaling","display_name":"Scaling","score":0.47579845786094666},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4683486819267273},{"id":"https://openalex.org/keywords/computational-science","display_name":"Computational science","score":0.3782978355884552},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.3513514995574951},{"id":"https://openalex.org/keywords/graphics","display_name":"Graphics","score":0.24536940455436707},{"id":"https://openalex.org/keywords/data-science","display_name":"Data science","score":0.1729801893234253}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8737368583679199},{"id":"https://openalex.org/C2778119891","wikidata":"https://www.wikidata.org/wiki/Q477690","display_name":"CUDA","level":2,"score":0.7502185106277466},{"id":"https://openalex.org/C2781335571","wikidata":"https://www.wikidata.org/wiki/Q2633544","display_name":"GPU cluster","level":3,"score":0.6004711985588074},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5695482492446899},{"id":"https://openalex.org/C79158427","wikidata":"https://www.wikidata.org/wiki/Q485396","display_name":"Analytics","level":2,"score":0.5434158444404602},{"id":"https://openalex.org/C2779851693","wikidata":"https://www.wikidata.org/wiki/Q183484","display_name":"Graphics processing unit","level":2,"score":0.5307334065437317},{"id":"https://openalex.org/C83283714","wikidata":"https://www.wikidata.org/wiki/Q121117","display_name":"Supercomputer","level":2,"score":0.5134585499763489},{"id":"https://openalex.org/C50630238","wikidata":"https://www.wikidata.org/wiki/Q971505","display_name":"General-purpose computing on graphics processing units","level":3,"score":0.5129708647727966},{"id":"https://openalex.org/C155281189","wikidata":"https://www.wikidata.org/wiki/Q3518150","display_name":"Tensor (intrinsic definition)","level":2,"score":0.5071218013763428},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.5033087134361267},{"id":"https://openalex.org/C99844830","wikidata":"https://www.wikidata.org/wiki/Q102441924","display_name":"Scaling","level":2,"score":0.47579845786094666},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4683486819267273},{"id":"https://openalex.org/C459310","wikidata":"https://www.wikidata.org/wiki/Q117801","display_name":"Computational science","level":1,"score":0.3782978355884552},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.3513514995574951},{"id":"https://openalex.org/C21442007","wikidata":"https://www.wikidata.org/wiki/Q1027879","display_name":"Graphics","level":2,"score":0.24536940455436707},{"id":"https://openalex.org/C2522767166","wikidata":"https://www.wikidata.org/wiki/Q2374463","display_name":"Data science","level":1,"score":0.1729801893234253},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C202444582","wikidata":"https://www.wikidata.org/wiki/Q837863","display_name":"Pure mathematics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/mm.2023.3256796","is_oa":false,"landing_page_url":"https://doi.org/10.1109/mm.2023.3256796","pdf_url":null,"source":{"id":"https://openalex.org/S59697426","display_name":"IEEE Micro","issn_l":"0272-1732","issn":["0272-1732","1937-4143"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IEEE Micro","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.44999998807907104}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W3130554079","https://openalex.org/W4292779060","https://openalex.org/W4297812065","https://openalex.org/W6778883912","https://openalex.org/W6843734122"],"related_works":["https://openalex.org/W2030707850","https://openalex.org/W2108266785","https://openalex.org/W2562576480","https://openalex.org/W4226437700","https://openalex.org/W3089221400","https://openalex.org/W1927238317","https://openalex.org/W4231763094","https://openalex.org/W2740639522","https://openalex.org/W2024548679","https://openalex.org/W1464113540"],"abstract_inverted_index":{"The":[0],"H100":[1],"Tensor":[2,35,38],"Core":[3],"GPU":[4],"is":[5],"NVIDIA\u2019s":[6],"latest":[7],"flagship":[8],"GPU.":[9],"It":[10],"has":[11],"been":[12],"designed":[13],"to":[14],"provide":[15],"industry":[16],"leading":[17],"performance":[18],"for":[19],"high-performance":[20],"computing,":[21],"artificial":[22],"intelligence,":[23],"and":[24,47],"data":[25],"analytics":[26],"datacenter":[27],"workloads.":[28],"Notable":[29],"new":[30,37,43],"features":[31],"include":[32],"a":[33,42],"fourth-generation":[34],"Core,":[36],"Memory":[39],"Accelerator":[40],"unit,":[41],"CUDA":[44],"cluster":[45],"capability,":[46],"HBM3":[48],"dynamic":[49],"random-access":[50],"memory.":[51]},"counts_by_year":[{"year":2026,"cited_by_count":10},{"year":2025,"cited_by_count":69},{"year":2024,"cited_by_count":45},{"year":2023,"cited_by_count":7}],"updated_date":"2026-04-24T08:23:43.765630","created_date":"2025-10-10T00:00:00"}
